Systems, devices, and methods for arc fault detection

1. A system comprising:

an arc fault detection circuit comprising:

a first zero crossing analysis sub-system comprising a counter configured to determine, for a first waveform, a first count of dips that occur between a first sequential pair of predetermined zero crossings of a second waveform; and

a count analysis sub-system comprising a comparator configured to request a trip of an electrical device responsive to a determination that said first count of dips is greater than a first count threshold, but below a second count threshold.

2. The system of claim 1 , further comprising:

a filter configured to derive said second waveform from said first waveform.

3. The system of claim 1 , further comprising:

a second zero crossing analysis sub-system configured to determine, for said first waveform, a second count of dips that occur between a second sequential pair of predetermined zero crossings of said second waveform.

4. The system of claim 1 , further comprising:

a low pass filter configured to remove high frequency signals from a signal that characterizes said first waveform, said high frequency signals characterized by a frequency greater than approximately two kilohertz.

5. The system of claim 1 , further comprising:

a dynamic range reference calculator configured to provide a reference signal indicative of a dynamic range of said first waveform.

6. The system of claim 1 , further comprising:

a reset circuit configured to determine that said first waveform does not indicate a fault based upon a determination that that an electrical measurement associated with said first waveform is below a predetermined electrical threshold.

7. The system of claim 1 , further comprising:

a slope reference calculator configured to ignore low-slope zero crossings comprised by said first waveform and characterized by a waveform slope below a predetermined slope threshold.

8. The system of claim 1 , further comprising:

a mask generation sub-system comprising:

a low pass filter configured to remove high frequency signals from a signal that characterizes said second waveform, said high frequency signals characterized by a frequency greater than approximately two kilohertz, said first zero crossing analysis sub-system configured to receive signals derived from said second waveform via said low pass filter.

9. The system of claim 1 , further comprising:

a mask generation sub-system comprising:

a peak detector configured to provide a peak signal to a compare/integrate circuit, said compare/integrate circuit adapted to change at least one predetermined threshold associated with tripping said electrical device, said at least one predetermined threshold associated with said count analysis sub-system.

10. The system of claim 1 , further comprising:

a mask generation sub-system comprising:

a zero crossing mask generator configured to generate an odd zero crossing mask and an even zero crossing mask, said first zero crossing analysis sub-system configured to receive at least one of said odd zero crossing mask and said even zero crossing mask.

11. The system of claim 1 , said first zero crossing analysis sub-system comprising:

a direct current removal circuit configured to remove a direct current offset from said first waveform.

12. The system of claim 1 , said first zero crossing analysis sub-system comprising:

an interruption counter configured to increment an interruption count responsive to a first received signal indicative of a zero crossing of said second waveform and a second received signal indicative of measurement of a magnitude associated with said first waveform exceeding a predetermined magnitude threshold.

13. The system of claim 1 , said first zero crossing analysis sub-system comprising:

an interruption counter configured to reset an interruption count responsive to said first count of dips exceeding said second count threshold.

14. The system of claim 1 , said first zero crossing analysis sub-system comprising:

a compare/integrate circuit configured to increment a trip count responsive to one or more of a first signal indicative of said first count, a second signal indicative of a slope associated with said first waveform exceeding a predetermined slope threshold, and a third signal indicative of a magnitude of a current reference.

15. The system of claim 1 , further comprising:

a second zero crossing analysis sub-system configured to determine, for said first waveform, a second count of dips that occur between a second sequential pair of predetermined zero crossings of said second waveform, said second zero crossing analysis sub-system comprising a direct current removal circuit configured to remove a direct current offset from said first waveform.

16. The system of claim 1 , further comprising:

a second zero crossing analysis sub-system configured to determine, for said first waveform, a second count of dips that occur between a second sequential pair of predetermined zero crossings of said second waveform, said second zero crossing analysis sub-system comprising an interruption counter configured to increment an interruption count responsive to a first received signal indicative of a zero crossing of said second waveform and a second received signal indicative of measurement of a magnitude associated with said first waveform exceeding a predetermined magnitude threshold.

17. The system of claim 1 , further comprising:

a second zero crossing analysis sub-system configured to determine, for said first waveform, a second count of dips that occur between a second sequential pair of predetermined zero crossings of said second waveform, said second zero crossing analysis sub-system comprising an interruption counter configured to reset an interruption count responsive to said first count of dips exceeding said second count threshold.

18. A method comprising:

producing an arc fault detection circuit comprising:

a first zero crossing analysis sub-system comprising a counter configured to determine, for a first waveform, a first count of dips that occur between a first sequential pair of predetermined zero crossings of a second waveform; and

a count analysis sub-system comprising a comparator configured to request a trip of an electrical device responsive to a determination that said first count of dips is greater than a first count threshold, but below a second count threshold.

19. A machine-readable medium comprising machine executable instructions for activities comprising:

requesting a trip of an electrical device associated with an electrical circuit responsive to a determination that a count of dips is greater than a first count threshold, but below a second count threshold, said count of dips determined, for a first waveform, between a sequential pair of predetermined zero crossings of a second waveform.