IP Library Granted Patent US 7,391,914
Granted Patent B2
US 7,391,914 · App. 11/381,839 · Granted Jun 24, 2008

Decoding of predicted DC coefficient without division

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,391,914
App. No.
11/381,839
Granted
Jun 24, 2008
Kind
B2
Abstract

A technique for eliminating the division in decoding a predicted DC coefficient includes calculating and storing the values of 1//DC_scalar in a table. This allows one to convert a division into a multiplication.

Claims (24)

1. A processing circuit comprising:

means for calculating all possible values for an inverted variable used in decoding predicted zero-frequency transform coefficients; and

means for storing all the values in a lookup table;

means for decoding the predicted zero-frequency transform coefficients with the values stored in the lookup table without using a divide unit.

2. The processing circuit of claim 1

where the means for calculating all possible values includes means for calculating an equivalence of all possible values for an inverted scalar value of a quantization parameter for a macro block calculated using rounding division; and

where the means for storing all the values in a lookup table comprises means for storing a value exactly equal to the inverse of the scalar value of a quantization parameter for a macro block for a predetermined level of precision.

3. The processing circuit of claim 1

where the means for calculating all possible values comprises means for calculating for each possible value of a scalar value of a quantization parameter for a macro block a value exactly equal to an inverse of the scalar value of quantization parameter for a macro block for a predetermined level of precision.

4. The processing circuit of claim 1

where the means for calculating all possible values comprises means for calculating, for a predetermined precision level, the zero-frequency coefficient of a macro block used for prediction purposes times the inverted variable used in decoding predicted zero-frequency transform coefficients for all values of the scalar value of a quantization parameter for a macro block.

5. The processing circuit of claim 1

where the means for calculating all possible values comprises means for calculating thirty-nine possible values for the inverted scalar value of a quantization parameter for a macro block; and

where the means for storing all the values in a lookup table comprises means for storing a value exactly equal to the inverse scalar of a quantization parameter for a macro block for a precision being used.

6. A processing circuit comprising:

means for storing all thirty-nine values of an inverted variable used in decoding a zero-frequency coefficient in a lookup table; and

means for calculating the zero-frequency coefficient using the lookup table to avoid using rounding division.

7. A processing circuit comprising:

means for storing all thirty-nine values of an inverted variable used in decoding zero-frequency coefficients calculated once off-line in a lookup table; and

means for calculating the zero-frequency coefficients without accessing a divide unit by repeatedly accessing the stored lookup table.

8. A system comprising:

encoded images;

a storage circuit to store a lookup table; and

a processor to decode a bit stream in the encoded images in software with said lookup table where a divide unit is not used when decoding predicted zero-frequency transform coefficients.

Assignments (1)
MERGER Recorded Nov 12, 2015
From: MEYER BROS. TECHNOLOGY GROUP LLC
To: GULA CONSULTING LIMITED LIABILITY COMPANY
Reel/Frame 037028/0283 →