Integrated circuit with reduced coupling noise
View Patent ↗In order for circuit blocks 1 to 3 composed by the CMOS process, and analog lines 5 −1 , 5 −2 , and 5 −3 connected thereto not to overlap on the layout, the analog lines 5 −1 and 5 −2 are wired so that such lines roundabout the layout of the AM/FM common circuit block 3 . Through this, the distance of the signal line within the AM/FM common circuit block 3 and the analog lines 5 −1 and 5 −2 can become as long as possible, the signal line within the AM/FM common circuit block 3 and the analog lines 5 −1 and 5 −2 would not be coupled via parasitic capacity, and mutual interference occurring between the signal line and the analog lines 5 −1 and 5 −2 can be suppressed. In another aspect, a semiconductor integrated circuit with a CMOS structure includes an analog circuit and a feedback loop, wherein an analog signal line for the feedback loop is wired outside a layout of the analog circuit.
1. A semiconductor integrated circuit composed by a CMOS structure, comprising: an analog circuit with a feedback loop; wherein an analog signal line for said feedback loop is wired outside a layout of said analog circuit.
2. A semiconductor integrated circuit comprising: an adder; an analog circuit that processes a signal output of said adder; and an analog signal line arranged to provide a feedback input to said adder from an output of said analog circuit, wherein said analog signal line is arranged outside a layout of said analog circuit.
3. An semiconductor integrated circuit, comprising: an adder; an analog circuit processing analog signal output from said adder; and an analog signal line to execute feed back input of the output signal to said adder from said analog circuit; wherein said analog signal line is arranged outside a layout of said analog circuit.
4. The semiconductor integrated circuit of claim 1 , wherein said analog signal line is configured to overcome parasitic capacity between the analog signal line and other signal lines of the semiconductor integrated circuit.
5. The semiconductor integrated circuit of claim 1 , wherein said analog signal line is configured to suppress mutual interference between the analog signal line and other signal lines of the semiconductor integrated circuit.
6. The semiconductor integrated circuit of claim 1 , wherein said analog signal line is configured to at least one of suppress deterioration of a quality of the analog signal that flows in the signal line and suppress erroneous operation of the semiconductor integrated circuit that occurs due to fluctuation of other signal lines on the semiconductor circuit.
7. The semiconductor integrated circuit of claim 2 , wherein said analog signal line is configured to overcome parasitic capacity between the analog signal line and other signal lines of the semiconductor integrated circuit.
8. The semiconductor integrated circuit of claim 2 , wherein said analog signal line is configured to suppress mutual interference between the analog signal line and other signal lines of the semiconductor integrated circuit.
9. The semiconductor integrated circuit of claim 2 , wherein said analog signal line is configured to at least one of suppress deterioration of a quality of the analog signal that flows in the signal line and suppress erroneous operation of the semiconductor integrated circuit that occurs due to fluctuation of other signal lines on the semiconductor circuit.
10. The semiconductor integrated circuit of claim 3 , wherein said analog signal line is configured to overcome parasitic capacity between the analog signal line and other signal lines of the semiconductor integrated circuit.
11. The semiconductor integrated circuit of claim 3 , wherein said analog signal line is configured to suppress mutual interference between the analog signal line and other signal lines of the semiconductor integrated circuit.
12. The semiconductor integrated circuit of claim 2 , wherein said analog signal line is configured to at least one of suppress deterioration of a quality of the analog signal that flows in the signal line and suppress erroneous operation of the semiconductor integrated circuit that occurs due to fluctuation of other signal lines on the semiconductor circuit.