Highspeed serial transmission system and a method for reducing jitter in data transfer on such a system

1 . A high-speed serial transmission system ( 10 ) comprising a transmitter ( 12 ), a transmission line ( 14 ) and a receiver ( 16 ), wherein the transmitter ( 12 ) comprising:

a bit-stream generator ( 18 ) for generating a predetermined pseudo random bit sequence (PRBS); and

a controllable phase distortion circuit ( 20 ) having an input ( 24 ) connected to the bit-stream generator ( 18 ) and a signal output ( 26 ) connected to the transmission line ( 14 );

the receiver ( 16 ) includes:

a sampling circuit ( 30 ) with a signal input ( 36 ) connected to the transmission line ( 14 ), a sampling clock input ( 38 ) and a data output ( 40 );

a clock recovery circuit ( 32 ) with a phase-locked loop circuit ( 42 ) and a controllable phase interpolator ( 44 ) that has signal inputs ( 45 ) connected to signal outputs of the phase-locked loop circuit ( 42 ) and an output ( 48 ) connected to the sampling clock input ( 38 ) of the sampling circuit ( 30 ); and

a bit-stream verification circuit ( 32 ) with an input ( 50 ) connected to the data output ( 40 ) of the sampling circuit ( 30 ) and an output ( 52 ) that controls the controllable phase interpolator, and

wherein an output ( 54 ) of the bit-stream verification circuit ( 34 ) controls the controllable phase distortion circuit ( 20 ) in the transmitter ( 12 ) in response to a bit error rate (BER) detected in the bit-stream received form the data output ( 40 ) of the sampling circuit ( 30 ) by comparison with the predetermined pseudo random bit sequence (PRBS).

2 . A method for reducing jitter in data transfer on a high-speed serial transmission system ( 10 ) according to claim 1 , the method comprising the steps of:

having the clock recovery circuit ( 32 ) locked in to an initial value for the phase of a sampling clock signal (CLK);

executing a test cycle comprising the steps of:

1) controlling the bit-stream generator ( 18 ) to generate a pseudo random bit sequence (PRBS);

2) sending the pseudo random bit sequence (PRBS) from the transmitter ( 12 ) via the transmission line ( 14 ) to the receiver ( 16 );

3) detecting an error rate (BER) in the received pseudo random bit sequence (PRBS) with the bit-stream verification unit ( 34 ); and

4) controlling the phase interpolator ( 44 ) to change the phase of the sampling clock signal (CLK) by one step;

sequentially repeating the test cycle for a number of different phase angle values;

calculating the effective eye opening for the data transmission arrangement ( 10 ) with the bit-stream verification circuit ( 34 ) from the detected error rates (BER); and

controlling the phase distortion circuit ( 20 ) by the bit-stream verification unit ( 34 ) to set up a configuration for minimum jitter according to the calculated effective eye opening.

3 . The method of claim 2 , wherein steps c) and d) include:

repeating the test cycle with the phase angle value being increased until a predetermined error rate occurs, the current phase angle value being marked as first boundary of an effective eye opening;

the phase angle being set back to the initial value again; and

repeating the test cycle with the phase angle value being decreased until a predetermined error rate occurs, the current phase angle value being marked as second boundary of an effective eye opening.

4 . A method for reducing jitter in data transfer on a high-speed serial transmission system ( 10 ) according to claim 1 , the method comprising the steps of:

having the clock recovery circuit ( 32 ) locked in to an initial value for the phase of the sampling clock signal (CLK);

controlling the phase distortion circuit ( 20 ) to set up a first configuration;

executing a test cycle comprising the steps of:

controlling the bit-stream generator ( 18 ) to generate a pseudo random bit sequence (PRBS);

sending the pseudo random bit sequence (PRBS) from the transmitter ( 12 ) via the transmission line ( 14 ) to the receiver ( 16 );

detecting an error rate in the received pseudo random bit sequence (PRBS) with the bit-stream verification unit ( 34 );

controlling the phase interpolator ( 44 ) to change the phase of the sampling clock signal (CLK) by one step;

sequentially repeating the test cycle for a number of different phase angle values;

calculating the effective eye opening for the setup configuration of the phase distortion circuit ( 20 ) from the detected error rates and storing the calculated value in the bit-stream verification unit ( 34 );

sequentially repeating steps b) through e), for all possible configurations of the phase distortion circuit ( 20 );

comparing the calculated effective eye opening values; and

controlling the phase distortion circuit ( 20 ) to set up the one configuration which established the maximum eye opening.