IP Library Granted Patent US 7,492,137
Granted Patent B2
US 7,492,137 · App. 11/384,861 · Granted Feb 17, 2009

Series regulator and differential amplifier circuit thereof

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Quick Facts
Patent No.
US 7,492,137
App. No.
11/384,861
Granted
Feb 17, 2009
Kind
B2
Abstract

A series regulator for supplying a stable output voltage to a load has a differential amplifier circuit and an output stage. The output stage has an output control transistor that supplies the output voltage in accordance with a control signal, and a voltage divider circuit that divides the output voltage and outputs the divided voltage. The differential input stage includes a differential pair (source-coupled pair) of two NMOS transistors, an NMOS transistor, and a current mirror circuit formed by PMOS transistors. The differential input stage detects a differential voltage between a reference voltage and the divided voltage output from the voltage divider circuit. The differential amplifier circuit also has an amplification stage including a PMOS transistor that has a resistor connected between its gate and drain and that has its drain connected to a node, and an NMOS transistor that supplies a current proportional to a constant current to the PMOS transistor. The series regulator/differential amplifier circuit allows both low output resistance and sufficient DC gain without increasing bias current.

Claims (24)

1. A series regulator for supplying a stable output voltage to a load, the series regulator comprising:

an output control transistor that supplies the output voltage in accordance with a control signal;

a voltage divider circuit that divides the output voltage and outputs the divided voltage; and

a differential amplifier circuit that outputs the control signal to the output control transistor in accordance with a differential voltage of difference between a preset reference voltage and the divided voltage output from the voltage divider circuit,

wherein the differential amplifier circuit includes:

a differential input stage for detecting the differential voltage between the reference voltage and the divided voltage output from the voltage divider circuit; and

an amplification stage having a first MOS transistor and a resistor having a predetermined resistance connected to the gate and the drain of the first MOS transistor, and a constant-current circuit connected in series with the first MOS transistor,

wherein the differential input stage includes a differential pair of second and third MOS transistors, with the drain of one of the second or third MOS transistor directly connected to the gate of the first MOS transistor,

wherein a connecting part between the first MOS transistor and the constant-current circuit serves as an output terminal of the amplification stage,

wherein the amplification stage converts current output from the differential input stage to a voltage to generate the control signal, which is output to the output control transistor,

wherein if the preset reference voltage is larger than the divided voltage, the amplification stage generates the control signal for increasing the output voltage to be output by the output control transistor,

wherein if the divided voltage is larger than the preset reference voltage, the amplification stage generates the control signal for decreasing the output voltage to be output by the output control transistor, and

wherein only the amplification stage exclusively outputs the control signal to the output control transistor when a differential voltage exists between the preset reference voltage and the divided voltage.

2. The series regulator according to claim 1 , wherein the sources of the second and third MOS transistors are coupled together, and wherein the reference voltage and the divided voltage output from the voltage divider circuit are input to the respective gates of the second and third MOS transistors to detect the differential voltage therebetween.

3. A differential amplifier circuit for outputting a differential signal, comprising:

a differential input stage for detecting a differential voltage between two voltage sources; and

an amplification stage having a first MOS transistor and a resistor having a predetermined resistance connected to the gate and the drain of the first MOS transistor, and a constant-current circuit connected in series with the first MOS transistor,

wherein the differential input stage includes a differential pair of second and third MOS transistors, with the drain of one of the second or third MOS transistor directly connected to the gate of the first MOS transistor,

wherein a connecting part between the first MOS transistor and the constant-current circuit serves as an output terminal of the amplification stage,

wherein the amplification stage converts current output from the differential input stage to a voltage to generate a control signal for controlling an output control transistor that outputs an output voltage,

wherein if the voltage from one of the two voltage sources is a larger than the voltage from the other voltage source, the amplification stage outputs the control signal for increasing the output voltage to be output by the output control transistor,

wherein if the voltage from the other voltage source is larger than the voltage from the one voltage source, the amplification stage outputs the control signal for decreasing the output voltage to be output by the output control transistor, and

wherein only the amplification stage exclusively outputs the control signal to the output control transistor when a differential voltage exists between the two voltage sources.

4. The differential amplifier circuit according to claim 3 , wherein the sources of the second and third MOS transistors are coupled together, and wherein the two voltage sources are input to the respective gates of the second and third MOS transistors to detect the differential voltage therebetween.

Assignments (4)
MERGER AND CHANGE OF NAME Recorded Aug 26, 2011
From: FUJI ELECTRIC SYSTEMS CO., LTD. (FES); FUJI TECHNOSURVEY CO., LTD. (MERGER BY ABSORPTION)
To: FUJI ELECTRIC CO., LTD.
Reel/Frame 026970/0872 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 20, 2010
From: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
To: FUJI ELECTRIC SYSTEMS CO., LTD.
Reel/Frame 024252/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INVENTOR EXECUTION DATE. PREVIOUSLY RECORDED ON REEL 017763 FRAME 0042. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT.. Recorded Jun 16, 2006
From: YAMADA, KOUHEI
To: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
Reel/Frame 017798/0594 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 12, 2006
From: YAMADA, KOUHEI
To: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
Reel/Frame 017763/0042 →