Sample rate converter
View Patent ↗A system and method for determining a clock rate of a digital phase lock loop is disclosed. The system includes a first input to receive a first clock signal, an output to provide a second clock signal, and a dividerless initial clock rate determination module to calculate an initial clock rate value based on an reciprocal of a pulse length of the first clock signal. In a particular embodiment, the dividerless initial clock rate determination module performs a piecewise linear operation to calculate the initial clock rate value.
1. A digital phase lock loop, comprising:
a first input to receive a first clock signal;
an output to provide a second clock signal, the second clock signal based on the first clock signal; and
a dividerless initial clock rate determination module to calculate an initial clock rate value based on a reciprocal of a measured pulse length of the first clock signal,
wherein the dividerless initial clock rate determination module comprises an accumulator and a comparator;
wherein in a first mode of operation the accumulator and the comparator are operable to calculate the initial clock rate value and wherein in a second mode of operation the accumulator and the comparator are operable to perform a digital filtering operation; and
wherein the dividerless initial clock rate determination module includes a register to store a step size, an adder to subtract the step size from an initial value stored in the accumulator, and wherein the comparator compares an output of the adder to a predetermined adjustment value, wherein the step size is adjusted based on an output of the comparator.
2. The digital phase lock loop of claim 1 , wherein a clock rate of the second clock signal is based on the initial clock rate value.
3. The digital phase lock loop of claim 1 , wherein the dividerless initial clock rate determination module performs a piecewise linear operation to calculate the initial clock rate value.
4. The digital phase lock loop of claim 3 , wherein the dividerless initial clock rate determination module performs the piecewise linear operation using a first step size during a first time period and using a second step size during a second time period.
5. The digital phase lock loop of claim 1 , wherein the first clock signal is a frame clock signal and further comprising:
a second input to receive a third clock signal that comprises a system clock signal.
6. The digital phase lock loop of claim 1 , wherein the second clock signal is provided to an interpolation filter.
7. The digital phase lock loop of claim 1 , further comprising:
a clock signal generator responsive to the first clock signal, wherein the clock signal generator generates the second clock signal.
8. A dividerless initial clock rate determination module, comprising
an input to receive a clock signal;
a dividerless logic module to determine an initial clock rate value by calculating a reciprocal of a measured pulse length of the clock signal; and
an output to provide the initial clock rate value;
wherein the dividerless logic module performs a piecewise linear calculation to calculate the initial clock rate value;
wherein the dividerless logic module comprises an accumulator to store an initial value, a register to store a step size, an adder to subtract the step size from the initial value stored in the accumulator, and a comparator to compare an output of the adder to a predetermined adjustment value, wherein the step size is adjusted based on an output of the comparator; and
wherein the predetermined adjustment value and the step size are chosen such that, at a particular system operating condition, the initial value and a slope of the piecewise linear calculation substantially match the reciprocal of the measured pulse length of the clock signal.
9. The dividerless initial clock rate determination module of claim 8 , wherein the step size is a power of two, and wherein the step size is adjusted using a shift operation.
10. The dividerless initial clock rate determination module of claim 8 , wherein the initial clock rate value is based on a value stored in the accumulator.
11. A sample rate converter, comprising:
an interpolation filter stage responsive to a digital input signal; and
a digital phase lock loop, including:
a first input to receive a first clock signal;
an output to provide a second clock signal, the second clock signal based on the first clock signal, wherein the interpolation filter stage is responsive to the second clock signal; and
a dividerless initial clock rate determination module to calculate an initial clock rate value based on reciprocal of a pulse length of the first clock signal;
wherein the dividerless initial clock rate determination module comprises an accumulator and a comparator;
wherein in a first mode of operation the accumulator and the comparator are operable to calculate the initial clock rate value and wherein in a second mode of operation the accumulator and the comparator are operable to perform a digital filtering operation; and
wherein the dividerless initial clock rate determination module includes a register to store a step size, an adder to subtract the step size from an initial value stored in the accumulator, and wherein the comparator compares an output of the adder to a predetermined adjustment value, wherein the step size is adjusted based on an output of the comparator.
12. The sample rate converter of claim 11 , wherein a rate of the second clock signal is based on the initial clock rate value.
13. The sample rate converter of claim 11 , wherein the dividerless initial clock rate determination module performs a piecewise linear operation to calculate the initial clock rate value.
14. The sample rate converter of claim 11 , wherein the interpolation filter stage provides a sample rate converted output to a switch of a television tuner.
15. A method of controlling a digital phase lock loop, comprising:
receiving a first edge of a pulse of a first clock signal;
performing a piecewise linear calculation to determine a clock rate of the digital phase lock loop based on a reciprocal of a pulse length of the pulse of the first clock signal;
providing a second clock signal having a frequency based on the determined clock rate;
storing an initial value at an accumulator;
storing a step size at a register;
subtracting, by an adder, the step size from the initial value stored at the accumulator; and
comparing an output of the adder to a predetermined adjustment value at a comparator, wherein the step size is adjusted based on an output of the comparator; and
wherein the predetermined adjustment value and the step size are chosen such that, at a particular system operating condition, the initial value and a slope of the piecewise linear calculation substantially match the reciprocal of the pulse length of the pulse of the first clock signal.
16. The method of claim 15 , wherein performing the piecewise linear calculation further includes decrementing the accumulator by a second step size during detection of a second portion of the pulse of the first clock signal.