Apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (IC)
View Patent ↗An apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (IC) includes operating a clock associated with the IC at a frequency (f TARGET ) at which IC operation is sought to be determined, measuring the actual clock period (T CLOCK — OUT ) at a clock output, scan testing the IC, measuring the actual clock period (T SCAN — CLOCK — OUT ) at the clock output, determining a delay by calculating the difference between T SCAN — CLOCK — OUT and T CLOCK — OUT , and compensating for the delay by increasing the clock frequency during scan test.
1. A method for compensating clock period elongation during scan testing in an integrated circuit (IC), comprising:
operating a clock associated with the IC at a frequency (f TARGET ) at which IC operation is sought to be determined;
measuring an actual clock period (T CLOCK — OUT ) during the operating step by observing a clock output signal at an externally observable clock output pad;
scan testing the IC;
measuring an actual clock period (T SCAN — CLOCK — OUT ) during the scan testing by observing the clock output signal at the externally observable clock output pad;
determining a delay by calculating the difference between the T SCAN — CLOCK — OUT and the T CLOCK — OUT ; and
compensating for the delay by increasing the clock frequency during the scan testing using an externally controllable clock input signal.
2. The method of claim 1 , further comprising testing specific circuitry on the IC using the functional testing and the scan testing.
3. The method of claim 2 , further comprising testing the same circuitry on the IC using the functional testing and the scan testing.
4. The method of claim 3 , wherein the functional testing utilizes built-in-self-test circuitry.
5. A method for compensating clock period elongation during scan testing in an integrated circuit (IC), comprising:
operating a clock associated with the IC at a frequency (f TARGET ) at which IC operation is sought to be determined;
functional testing the IC to determine a frequency corresponding to a functional test pass/fail boundary (f FUNCTIONAL — TEST );
scan testing the IC to determine the highest clock frequency (f SCAN ) at which the IC passes the scan test;
determining a delay by calculating the difference between the f SCAN during the scan testing and the f FUNCTIONAL — TEST during the functional testing; and
compensating for the delay by increasing the clock frequency during the scan testing using an externally controllable clock input signal.
6. The method of claim 5 , further comprising testing specific circuitry on the IC using the functional testing and the scan testing.
7. The method of claim 6 , further comprising testing the same circuitry on the IC using the functional testing and the scan testing.
8. The method of claim 7 , wherein the functional testing uses built-in-self-test circuitry.