IP Library Granted Patent US 7,587,005
Granted Patent B2
US 7,587,005 · App. 11/390,155 · Granted Sep 8, 2009

Exploiting known padding data to improve block decode success rate

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Quick Facts
Patent No.
US 7,587,005
App. No.
11/390,155
Granted
Sep 8, 2009
Kind
B2
Abstract

A method and system of decoding a convolutionally encoded data block having known padding bits. A Viterbi decoder is constrained to a state corresponding to k−1 padding bits immediately adjacent to data bits of the data block, where k is a constraint length of a convolution encoder used to encode the data block. Symbols of the encoded data block that have influence only from the padding bits are discarded.

Claims (27)

1. A method of decoding a convolutionally encoded data block having known padding bits, the method for use in a controller and comprising steps of:

constraining a Viterbi decoder to a state corresponding to k−1 padding bits immediately adjacent data bits of the data block, where k is a constraint length of a convolutional encoder used to encode the data block; and

discarding symbols of the encoded data block that have influence only from the padding bits,

wherein the Viterbi decoder is connected to the controller.

2. A method as claimed in claim 1 , wherein at least a portion of the padding bits are prepended to the data bits, and wherein the step of constraining the Viterbi decoder comprises a step of constraining a Start state of the decoder to a state corresponding to the last k−1 padding bits prepending the data bits.

3. A method as claimed in claim 2 , wherein the step of discarding symbols of the encoded data block comprises steps of:

latching the known padding bits of the data block into a shift register of the Viterbi decoder, without decoding the known padding bits; and

starting the Viterbi decoder at the first symbol after the first S=n/R symbols of the encoded data block, where n is the number of prepended padding bits, and R is the code rate of the convolutional encoder.

4. A method as claimed in claim 1 , wherein at least a portion of the padding bits are appended to the data bits, and wherein the step of constraining the Viterbi decoder comprises a step of constraining an End state of the decoder to a state corresponding to the first k−1 padding bits appending the data bits.

5. A method as claimed in claim 4 , wherein the step of discarding symbols of the encoded data block comprises steps of:

processing a sufficient number of symbols of the encoded data block through the Viterbi decoder to flush the bit corresponding to the last data bit out of the shift register; and

discarding any remaining symbols of the data block.

6. A method as claimed in claim 5 , wherein the step of processing a sufficient number of symbols of the encoded data block through the Viterbi decoder comprises a step of processing the first e=(N−n) (k−1) bits of the encoded data block through the Viterbi decoder, wherein N is the total number of bits capacity of the data block, and n is the total number of padding bits appended to the data bits.

7. A system for decoding a convolutionally encoded data block having known padding bits, the system comprising:

a Viterbi decoder; and

a controller adapted to:

constrain the Viterbi decoder to a state corresponding to k−1 padding bits immediately adjacent data bits of the data block, where k is a constraint length of a convolution encoder used to encode the data block; and

discard symbols of the encoded data block that have influence only from the padding bits.

8. A system as claimed in claim 7 , wherein at least a portion of the padding bits are prepended to the data bits, and wherein the controller is adapted to constraining a start state of the decoder to a state corresponding to the last k−1 padding bits prepending the data bits.

9. A system as claimed in claim 8 , wherein the controller is adapted to discard symbols of the encoded data block that have influence only from the padding bits by:

disabling operation of the Viterbi decoder while latching the known padding bits of the data block into a shift register of the Viterbi decoder; and

enabling the Viterbi decoder at the first symbol after the first S=n/R symbols of the encoded data block, where n is the number of prepended padding bits, and R is the code rate of the convolutional encoder.

10. A system as claimed in claim 7 , wherein at least a portion of the padding bits are appended to the data bits, and wherein the controller is adapted to constrain an End state of the decoder to a state corresponding to the first k−1 padding bits appending the data bits.

11. A system as claimed in claim 10 , wherein the controller is adapted to discard symbols of the encoded data block that have influence only from the padding bits by:

processing a sufficient number of symbols of the encoded data block through the Viterbi decoder to flush the bit corresponding to the last data bit out of the shift register; and

discarding any remaining symbols of the data block.

12. A system as claimed in claim 11 , wherein processing a sufficient number of symbols of the encoded data block through the Viterbi decoder comprises processing the first e=(N−n)+(k−1) bits of the encoded data block through the Viterbi decoder, wherein N is the total number of bits capacity of the data block, and n is the total number of padding bits appended to the data bits.

Assignments (4)
NUNC PRO TUNC ASSIGNMENT Recorded Jun 19, 2023
From: BLACKBERRY LIMITED
To: MALIKIE INNOVATIONS LIMITED
Reel/Frame 064269/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 16, 2023
From: BLACKBERRY LIMITED
To: MALIKIE INNOVATIONS LIMITED
Reel/Frame 064104/0103 →
CHANGE OF NAME Recorded Nov 5, 2014
From: RESEARCH IN MOTION LIMITED
To: BLACKBERRY LIMITED
Reel/Frame 034176/0557 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 25, 2006
From: TRAN, PHAT
To: RESEARCH IN MOTION LIMITED
Reel/Frame 018002/0193 →