Distributed processing architecture with scalable processing layers
View Patent ↗The present invention is a system on chip having a scalable, distributed processing architecture and memory capabilities through a plurality of parallel processing layers. In one embodiment, the processor comprises a plurality of processing layers, a processing layer controller, and a central direct memory access controller. The processing layer controller manages the scheduling of tasks and distribution of processing tasks to each processing layer. Within each processing layer, a plurality of pipelined processing units (Pus), specially designed for conducting a defined set of processing tasks, are in communication with program memories and data memories.
1. A media processor for the processing of media based upon instructions, comprising: a single chip comprising a) a first processing layer wherein said first processing layer has at least two processing units, at least one program memory, and at least one data memory, each of said processing units, program memory, and data memory being in communication with one another, b) a second processing layer wherein said second processing layer operates in parallel to said first processing layer and has at least two processing units, at least one program memory, and at least one data memory, each of said processing units, program memory, and data memory being in communication with one another, wherein at least one of said two processing units in each of said first and second processing layers performs line echo cancellation functions on received data and wherein at least one of said two processing units in each of said first and second processing layers performs encoding or decoding functions on received data; and e) a task scheduler adapted to receive a plurality of tasks from a source and distributing said tasks to each of said first and second processing layers for execution in a parallel, pipelined manner.
2. The media processor of claim 1 , wherein the single chip further comprises a direct memory access controller for handling data transfers, each of said transfers having a size and a direction, from at least one data memory having an address and a plurality of external memory units, each having an address.
3. The media processor of claim 2 , wherein said transfers between at least one data memory and at least one external memory occur by utilizing the address of the data memory, the address of the external memory, the size of the transfer, and the direction of the transfer.
4. The media processor of claim 1 , wherein the task scheduler is in communication with an external memory.
5. The media processor of claim 1 , wherein the single chip further comprises an interface for the receipt and transmission of data and control signals.
6. The media processor of claim 5 , wherein the interface comprises a UTOPIA-compatible interface.
7. The media processor of claim 5 , wherein the interface comprises a time division multiplex-compatible interface.
8. The media processor of claim 1 , wherein the processing unit designed to perform encoding or decoding functions comprises an arithmetic and logic unit, multiply and accumulate unit, barrel shifter, and normalization unit.
9. The media processor of claim 1 , wherein each of said first and second processing layers comprise a third processing unit wherein said third processing unit performs voice activity detection and tone signaling functions.
10. The media processor of claim 9 , wherein the third processing unit comprises a plurality of single-cycle multiply and accumulate units operating with an address generation unit and an instruction decoder.