IP Library Granted Patent US 7,356,652
Granted Patent B1
US 7,356,652 · App. 11/390,680 · Granted Apr 8, 2008

System and method for selectively storing bus information associated with memory coherency operations

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Quick Facts
Patent No.
US 7,356,652
App. No.
11/390,680
Granted
Apr 8, 2008
Kind
B1
Abstract

A manner for judiciously snooping or otherwise monitoring bus operations associated with maintaining cache or other memory coherency in a computing system. A bus snoop information storage mode is established that identifies information pertaining to the bus snoop operations used to maintain memory coherency. The bus snoop information storage mode is selectable, relative to possible other modes. When the bus snoop information storage mode is activated, the information pertaining to the bus snoop operations occurring in connection with bus snoop stall cycles is disregarded, while the current state of the information pertaining to the bus snoop operations upon completion of the bus snoop operations is stored.

Claims (28)

1. A method for recording pertinent information associated with bus snoop operations used to maintain memory coherency in a computing system, comprising:

establishing a bus snoop information storage mode that identifies information pertaining to the bus snoop operations used to maintain memory coherency in the computing system;

facilitating controllable activation of at least the bus snoop information storage mode; and

when the bus snoop information storage mode is activated, disregarding the information pertaining to the bus snoop operations occurring in connection with bus snoop stall cycles, and recording a current state of the information pertaining to the bus snoop operations upon completion of the bus snoop operations.

2. The method of claim 1 , further comprising determining the completion of the bus snoop operations by monitoring for memory hit and miss indicators for each of agent having an associated memory for which the memory coherency is to be maintained, and recognizing completion of the bus snoop operations when each of the agents have respectively indicated a memory hit or miss.

3. The method of claim 1 , further comprising determining the occurrence of bus snoop stall cycles by monitoring for memory hit and miss indicators for each of agent having an associated memory for which the memory coherency is to be maintained, and recognizing the bus snoop stall cycles where any of the agents have not yet indicated a memory hit or miss.

4. The method of claim 3 , further comprising repeatedly monitoring for the memory hit and miss indicators for each of the agents until all of the agents have indicated a memory hit or miss, and recognizing completion of the bus snoop operations when each of the agents has indicated a memory hit or miss.

5. The method of claim 1 , further comprising designating a plurality of information storage modes, each identifying a different set of information of the computing system to be monitored, wherein at least one of the information storage modes is the bus snoop information storage mode.

6. The method of claim 5 , wherein establishing a bus snoop information storage mode comprises designating at least one of the plurality of information storage modes as the bus snoop information storage mode.

7. The method of claim 1 , wherein recording a current state of the information comprises storing the current state of the information pertaining to the bus snoop operations when the bus snoop operations have completed without any of the bus snoop stall cycles.

8. The method of claim 1 , wherein disregarding the information pertaining to the bus snoop operations occurring in connection with bus snoop stall cycles comprises monitoring both the information pertaining to the bus snoop operations occurring in connection with bus snoop stall cycles and the information pertaining to the bus snoop operations upon completion of the bus snoop operations, and storing only the information pertaining to the bus snoop operations upon completion of the bus snoop operations.

9. The method of claim 1 , wherein disregarding the information pertaining to the bus snoop operations occurring in connection with bus snoop stall cycles comprises monitoring only the information pertaining to the bus snoop operations upon completion of the bus snoop operations, and recording the current state of the information.

10. The method of claim 1 , wherein facilitating controllable activation of at least the bus snoop information storage mode comprises enabling activation of the bus snoop information storage mode via a dynamic scan register.

11. The method of claim 1 , wherein recording a current state of the information comprises storing the current state of the information pertaining to the bus snoop operations as an entry in a multi-entry memory device, and further comprising incrementing the multi-entry memory to the next available entry location upon recording the current state of the information.

12. An apparatus for selectively storing information associated with bus snoop operations used to maintain cache coherency in a computing system having multiple agents each associated with at least one respective cache memory for which the cache coherency is to be maintained, the apparatus comprising:

a memory;

a history control register to receive and store data indicative of a bus snoop information storage mode; and

a history control processing arrangement coupled to the history control register and to the memory, and having an interface to receive the information associated with the bus snoop operations, wherein the history control processing arrangement is configured to activate the bus snoop information storage mode based on the data in the history control register, and in response to prohibit the memory from storing a first subset of the information corresponding to bus snoop operation data occurring in connection with bus snoop stall cycles and to enable the memory to store a second subset of the information corresponding to bus snoop operation data occurring in connection with completed bus snoop operations.

13. The apparatus of claim 12 , further comprising a user input device coupled to the history control register to facilitate user entry of the data indicative of the bus snoop information storage mode.

14. The apparatus of claim 12 , wherein the history control register comprises a dynamic scan register to serially receive the data indicative of the bus snoop information storage mode.

15. The apparatus of claim 12 , further comprising a computing device coupled to the history control register to retrieve the second subset of the information from the memory.

16. The apparatus of claim 12 , wherein the memory comprises an enable input to receive signals enabling or prohibiting storing of the information, and wherein the processor is configured to prohibit the memory from storing the first subset of the information by providing a first a signal to the enable input, and to enable the memory to store the second subset of the information by providing a second signal to the enable input.

17. A system for selectively storing information associated with bus snoop operations used to maintain cache coherency in a multi-agent computing system, comprising:

means for receiving a plurality of indicators each indicative of a respective information storage mode;

means for activating a bus snoop information storage mode in response to the data receiving means having received a particular one of the indicators;

means for prohibiting storage of a first set of the information associated with the bus snoop operations that occurs in connection with bus snoop stall cycles affecting any of the agents in the multi-agent computing system, when the bus snoop information storage mode has been activated;

means for enabling storage of a second set of the information associated with the bus snoop operations that occurs in connection with completion of the bus snoop operations when all of the bus snoop stall cycles have ceased, when the bus snoop information storage mode has been activated; and

means, coupled to the means for enabling storage, for storing the second set of the information.

Assignments (11)
AMENDED AND RESTATED PATENT SECURITY AGREEMENT Recorded Jun 27, 2025
From: UNISYS CORPORATION; UNISYS HOLDING CORPORATION; UNISYS NPL, INC.; UNISYS AP INVESTMENT COMPANY I
To: COMPUTERSHARE TRUST COMPANY, N.A., AS COLLATERAL TRUSTEE
Reel/Frame 071759/0527 →
RELEASE OF SECURITY INTEREST Recorded Oct 28, 2020
From: WELLS FARGO BANK, NATIONAL ASSOCIATION
To: UNISYS CORPORATION
Reel/Frame 054231/0496 →
RELEASE OF SECURITY INTEREST Recorded Nov 9, 2017
From: WELLS FARGO BANK, NATIONAL ASSOCIATION (SUCCESSOR TO GENERAL ELECTRIC CAPITAL CORPORATION)
To: UNISYS CORPORATION
Reel/Frame 044416/0358 →
SECURITY INTEREST Recorded Oct 6, 2017
From: UNISYS CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 044144/0081 →
PATENT SECURITY AGREEMENT Recorded Apr 27, 2017
From: UNISYS CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL TRUSTEE
Reel/Frame 042354/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 26, 2013
From: DEUTSCHE BANK TRUST COMPANY AMERICAS, AS COLLATERAL TRUSTEE
To: UNISYS CORPORATION
Reel/Frame 030082/0545 →
RELEASE OF SECURITY INTEREST Recorded Mar 15, 2013
From: DEUTSCHE BANK TRUST COMPANY
To: UNISYS CORPORATION
Reel/Frame 030004/0619 →
SECURITY AGREEMENT Recorded Jun 27, 2011
From: UNISYS CORPORATION
To: GENERAL ELECTRIC CAPITAL CORPORATION, AS AGENT
Reel/Frame 026509/0001 →
PATENT SECURITY AGREEMENT (JUNIOR LIEN) Recorded Oct 13, 2009
From: UNISYS CORPORATION
To: DEUTSCHE BANK TRUST COMPANY AMERICAS, AS COLLATERAL TRUSTEE
Reel/Frame 023364/0098 →
PATENT SECURITY AGREEMENT (PRIORITY LIEN) Recorded Oct 12, 2009
From: UNISYS CORPORATION
To: DEUTSCHE BANK TRUST COMPANY AMERICAS, AS COLLATERAL TRUSTEE
Reel/Frame 023355/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 28, 2006
From: DEW, MARSHALL R.; SUTTER, STEPHEN; TRAN, HOWARD HUY P.; WILLAIMS, DAVID P.
To: UNISYS CORPORATION
Reel/Frame 017729/0725 →