IP Library Granted Patent US 7,627,058
Granted Patent B2
US 7,627,058 · App. 11/390,761 · Granted Dec 1, 2009

Alternating quadratures differential binary phase shift keying modulation and demodulation method

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Quick Facts
Patent No.
US 7,627,058
App. No.
11/390,761
Granted
Dec 1, 2009
Kind
B2
Abstract

A method of performing alternating quadratures differential binary phase shift keying modulation involves limiting phase changes between adjacent in time modulator output symbols to ±90 °, and transmitting modulator input data by 0° and 180° phase differences between non-adjacent in time modulator output symbols.

Claims (47)

1. A method of operating a modulator by performing alternating quadratures differential binary phase shift keying modulation, comprising the steps of:

limiting phase changes between adjacent in time output symbols produced by the modulator to ±90°; and

transmitting data input to the modulator by 0° and 180° phase differences between non-adjacent in time output symbols produced by the modulator.

2. The method of claim 1 , further comprising the steps of:

separating modulator input data bits into first and second parity modulator input data bits;

converting the first and second parity modulator input data bits into 2-bit symbols;

sending the 2-bit symbols corresponding to the first parity input data bits to an in-phase channel and the 2-bit symbols corresponding to the second parity modulator input data bits to a quadrature channel;

performing differential polarity modulation of the 2-bit symbols corresponding to the first parity modulator input data bits in an in-phase channel and the 2-bit symbols corresponding to the second parity modulator input data bits in a quadrature channel and obtaining differentially modulated 2-bit symbols in both in-phase and quadrature channels; and

performing interpolating and pulse shaping digital filtering of the differentially modulated 2-bit symbols in both in-phase and quadrature channels.

3. The method of claim 1 , further comprising the steps of:

converting modulator input data bits into 2-bit symbols;

separating first and second parity 2-bit symbols;

sending the first parity 2-bit symbols to an in-phase channel and the second parity 2-bit symbols to a quadrature channel;

performing differential polarity modulation of the first parity 2-bit symbols in an in-phase channel and the second parity 2-bit symbols in a quadrature channel and obtaining differentially modulated 2-bit symbols in both in-phase and quadrature channels; and

performing interpolating and pulse shaping digital filtering of the differentially modulated 2-bit symbols in both in-phase and quadrature channels.

4. The method of claim 1 , further comprising the steps of:

differentially encoding same parity bits in a modulator input data stream;

sending the differentially encoded data bits to both in-phase and quadrature channels;

converting the differentially encoded data bits into 2-bit symbols in one of the channels;

modulo 2 adding a sequence of alternating ones and zeros to the differentially encoded data bits in the other channel;

converting the modulo 2 sums into 2-bit symbols; and

performing interpolating and pulse shaping digital filtering of the 2-bit symbols in both in-phase and quadrature channels.

5. The method of claim 1 , further comprising the steps of:

differentially encoding same parity bits in a modulator input data stream;

converting the differentially encoded data bits into 2-bit symbols;

converting the bits of a sequence of alternating ones and zeros into 2-bit symbols;

sending 2-bit symbols corresponding to the differentially encoded input bits to both in-phase and quadrature channels;

multiplying the 2-bit symbols corresponding to the differentially encoded input bits by the 2-bit symbols corresponding to the sequence of alternating ones and zeros and obtaining 2-bit products in one of the channels;

performing interpolating and pulse shaping digital filtering of the 2-bit products in the channel where the multiplication is carried out; and

performing interpolating and pulse shaping digital filtering of the 2-bit symbols corresponding to the differentially encoded input bits in the other channel.

6. The method of claim 2 , in which the step of performing differential polarity modulation in each channel comprises the step of:

multiplying input 2-bit symbols of a differential polarity modulator by its output 2-bit symbols that are delayed by the time equal to the length of two modulator input bits.

7. The method of claim 3 , in which the step of performing differential polarity modulation in each channel comprises the step of:

multiplying input 2-bit symbols of a differential polarity modulator by its output 2-bit symbols that are delayed by the time equal to the length of two modulator input bits.

8. The method of claim 4 , in which the differential encoding step comprises the step of:

modulo 2 summing the differential encoder input bits and its output bits delayed by the time equal to the length of two modulator input bits.

9. The method of claim 5 , in which the differential encoding step comprises the step of:

modulo 2 summing the differential encoder input bits and its output bits delayed by the time equal to the length of two modulator input bits.

10. A method of operating a demodulator, comprising the steps of:

receiving in the demodulator first and second parity modulated input signals, the phase shift between adjacent in time different parity modulated input signals being limited to ±90° and the phase difference between adjacent in time same parity modulated input signals being 0° or 180°; and

producing output data from the demodulator in response to the phase differences between same parity modulated input signals.

11. A method of noncoherent demodulation of alternating quadratures differential binary phase shift keying signals, in accordance with claim 10 , in which the producing step comprises the steps of:

forming in-phase and quadrature components of a received signal;

separately integrating in-phase and quadrature components of this signal during the time equal to the length of the modulator input data bit;

differentially demodulating the same parity input symbols by separate multiplying a current output signal of each integrator by its output signal delayed by the time equal to the length of two modulator input bits in the in-phase and quadrature channels of a receiver;

summing the products obtained in the in-phase and quadrature channels; and

making a hard decision about a received symbol by utilizing only the sign of the sum or a soft decision about the received symbol by utilizing both sign and value of the sum.