Method and device for reduced read latency of non-volatile memory
View Patent ↗Systems, apparatuses and methods for controlling access operations in a memory device that may include a memory controller(s) and memory. Commands, registers and/or other mechanisms may be defined to be supported by the memory device, where such commands, registers, and/or other mechanisms facilitate the control of read and write/erase operations to allow these operations to be performed simultaneously. Thus, a write and/or erase operation may be initiated on a first memory, a read operation initiated by a set of commands on a second memory, wherein the read and write/erase operations are performed substantially at the same time.
1. A method for controlling access operations in a non-volatile memory device, the non-volatile memory device comprising a memory controller and at least one NAND type memory chip, wherein said NAND memory chip has suspend capability, the method comprising:
suspending at least one write and/or erase operation on a first memory unit via a set of commands by said memory controller; and subsequently
initiating a read operation on a second memory unit via a set of commands including a read command for initiating said read operation by said memory controller wherein said read command includes a priority argument; and
deciding if an ongoing write/erase operation is to be suspended, on the basis of said priority argument.
2. The method of claim 1 said non-volatile memory device comprising at least two NAND flash memory chips, wherein said first and second memory units correspond to a first and a second NAND memory chip.
3. The method of claim 1 wherein said at least one non-volatile memory chip comprises a NAND flash memory chip capable of simultaneous read-while-write access, wherein said first memory unit is a first memory block and said second memory unit is a second memory block on said at least one memory chip.
4. The method of claim 3 , said non-volatile memory device comprising at least two NAND memory chips, wherein said first and second memory blocks are memory blocks of two different NAND chips.
5. The method of claim 1 further comprising receiving at least one of said set of commands from an external host device by said memory controller.
6. A computer program product comprising program code means stored on a computer readable medium for carrying out the operations of claim 1 when executed on a computing or processing arrangement.
7. The method of claim 1 , the method further comprising deciding if an ongoing data transfer to and/or from is to be suspended, on the basis of said priority argument.
8. A method for controlling access operations in a non-volatile memory device, the non-volatile memory device comprising a memory controller and at least one NAND type memory chip, wherein said NAND memory chip has suspend capability, the method comprising:
suspending at least one write and/or erase operation on a first memory unit via a set of commands by said memory controller; and subsequently
initiating a read operation on a second memory unit via a set of commands including a read command for initiating said read operation by said memory controller wherein said read command automatically triggers suspension of any ongoing write/erase operation and includes a suspend argument, and wherein said suspending any ongoing write/erase operation is performed responsive to said suspend argument.
9. The method of claim 8 , wherein said read command automatically triggers suspension of any data transfer to and from said flash memory device.
10. A computer readable storage medium encoded with a computer program comprising code for carrying out the operations of claim 8 when executed on a computing or processing arrangement.
11. A non-volatile memory device, comprising a memory controller and at least one non-volatile memory chip, wherein first and second memory units are provided, wherein said memory controller is configured to initiate a write and/or erase operation on said first memory unit; and is further configured to initiate a read operation on said second memory unit via a set of commands, and wherein said memory controller is adapted to carry out said read and said write and/or erase operations simultaneously and is further configured to detect an additional priority argument or suspend argument in said set of commands.
12. The memory device of claim 11 , wherein said memory controller is further configured to suspend access operations to a memory unit.
13. The memory device of claim 11 , wherein said first and second memory units correspond to separate blocks of at least one NAND flash memory chip.
14. The memory device of claim 11 , comprising at least two NAND flash memory chips, wherein said first and second memory units correspond to a first and a second NAND flash memory chip.
15. A device according to claim 11 comprising:
means for initiating a write and/or erase operation on a first memory unit of said memory device;
means for initiating a read operation on a second memory unit of said memory device; and
means for controlling said read and write/erase operations to be performed simultaneously.
16. A host device comprising:
a data transfer unit configured to communicate data between a host device and a flash memory device, a command unit configured to issue control commands including at least one command including a priority or suspend argument to said flash memory device; and
wherein said host device is capable of controlling said flash memory device such that a second access operation is initiated on said flash memory device before a first ongoing access operation is completed.
17. A memory module comprising a memory controller and at least one nonvolatile memory chip, wherein first and second memory units are provided,
wherein said memory controller is configured to initiate a write and/or erase operation on said first memory unit; and is further configured to initiate a read operation on said second memory unit via a set of commands; and
wherein said memory controller is adapted to perform said read and said write and/or erase operations simultaneously and is further configured to detect a priority argument or suspend argument in said set of commands.
18. A system comprising:
a memory module including,
a memory controller and at least one nonvolatile memory chip, wherein first and second memory units are provided;
wherein said memory controller is configured to initiate a write and/or erase operation on said first memory unit; and is further configured to initiate a read operation on said second memory unit via a set of commands;
wherein said memory controller is adapted to perform said read and said write and/or erase operations simultaneously and is further configured to detect a priority argument or suspend argument in said set of commands; and
a host device including,
a data transfer unit configured to communicate data between said host device and a flash memory device, a command unit configured to issue control commands to said flash memory device; and
wherein said host device is capable of controlling said flash memory device such that a second access operation is initiated on said flash memory device before a first ongoing access operation is completed.