Method and system for phase and byte alignment on a multiplexed high speed bus

1. A multiplexing system, comprising:

a first integrated circuit device, the first integrated circuit device generating a plurality of serialized data signals;

a second integrated circuit device in electrical communication with the first integrated circuit device, the second integrated circuit device including a multiplexer operable to generate a multiplexed output signal from the plurality of serialized data signals received from the first integrated circuit device; and

a phase data and byte snapshot back channel transmitted from the second integrated circuit device to the first integrated circuit device, the phase data and byte snapshot back channel carrying phase information regarding bit alignment for each of the plurality of serialized data signals and periodic snapshots regarding byte alignment of the serialized data signals, the phase data and byte snapshot back channel being used by the first integrated circuit device to adjust the phase of each of the plurality of serialized data signals to preserve bit and byte alignment.

2. The multiplexing system of claim 1 , wherein the first integrated circuit device is a CMOS device.

3. The multiplexing system of claim 1 , wherein the second integrated circuit device is one of a bipolar and GaAs device.

4. The multiplexing system of claim 1 , wherein each of the plurality of serialized data signals is a 10 Gbit/Sec. signal and the multiplexed output signal is a 40 Gbit/Sec. signal.

5. The multiplexing system of claim 1 , wherein the second integrated circuit device detects the phase of each of the plurality of serialized data signals and takes the periodic snapshots of the serialized data signals.

6. The multiplexing system of claim 5 , wherein the second integrated circuit device includes a phase detector to detect the phase of each of the plurality of serialized data signals, the phase detector generating the phase data signal for a corresponding phase state of each of the plurality of serialized data signals, the phase data signal being used by the first integrated circuit device to adjust the phase of the corresponding serialized data signals to achieve bit alignment within each of the serialized data signals.

7. The multiplexing system of claim 5 , wherein the second integrated circuit device includes a master clock retime and snapshot device to retime each of the serialized data signals onto a master clock and capture intermittent data snapshots from each of the serialized data signals, the intermittent data snapshots being used by the first integrated circuit device to achieve byte alignment among the plurality of serialized data signals.

8. The multiplexing system of claim 1 , wherein the multiplexer is arranged to drive the output signal for transmission to an optical transmitter.

9. The multiplexing system of claim 1 , wherein the first integrated circuit includes a digital filter, the digital filter analyzing the phase data and generating phase correction data for subsequent transmission to the second integrated circuit.

10. The multiplexing system of claim 1 , wherein the first integrated circuit includes a byte shifter, the byte shifter aligning the bits of a corresponding serialized data signal by shifting bits until the snapshot data returned from the second integrated circuit device matches an intended byte alignment.

11. The multiplexing system of claim 10 , wherein the first integrated circuit includes a byte comparator, the byte comparator comparing the intended byte alignment with the alignment in the snapshot data to determine if the two are the same.

12. The multiplexing system of claim 11 , wherein the first integrated circuit further includes a SERDES device in electrical communication with the byte shifter, the SERDES device serializing the byte aligned data and transmitting a serialized data signal to the second integrated circuit device.

13. A multiplexing method, comprising:

generating a plurality of serialized data signals in a first integrated circuit device;

receiving the plurality of serialized data signals in a second integrated circuit device;

generating a multiplexed output signal from the plurality of serialized data signals; and

transmitting a phase data and byte snapshot back channel from the second integrated circuit device to the first integrated circuit device, the phase data and byte snapshot back channel carrying phase information regarding bit alignment for each of the plurality of serialized data signals and periodic snapshots regarding byte alignment of the serialized data signals; and using the first integrated circuit device to adjust the phase of each of the plurality of serialized data signals to preserve bit and byte alignment.

14. The multiplexing method of claim 13 , wherein the first integrated circuit device is a CMOS device.

15. The multiplexing method of claim 13 , wherein the second integrated circuit device is one of a bipolar and GaAs device.

16. The multiplexing method of claim 13 , wherein each of the plurality of serialized data signals is a 10 Gbit/Sec. signal and the multiplexed output signal is a 40 Gbit/Sec. signal.

17. The multiplexing method of claim 13 , further comprising using the second integrated circuit device to detect the phase of each of the plurality of serialized data signals and take the periodic snapshots of the serialized data signals.

18. The multiplexing method of claim 17 , further including:

detecting the phase of each of the plurality of serialized data signals; and

generating the phase data signal for a corresponding phase state of each of the plurality of serialized data signals; and

adjusting the phase of the corresponding serialized data signals to achieve bit alignment within each of the serialized data signals.

19. The multiplexing method of claim 17 , further including:

retiming each of the serialized data signals onto a master clock;

capturing intermittent data snapshots from each of the serialized data signals; and

using the first integrated circuit device to achieve byte alignment among the plurality of serialized data signals.

20. The multiplexing method of claim 13 , further including:

analyzing the phase data; and

generating phase correction data for subsequent transmission to the second integrated circuit.

21. The multiplexing method of claim 13 , the method further including aligning the bits of a corresponding serialized data signal by shifting bits until the snapshot data returned from the second integrated circuit device matches an intended byte alignment.

22. The multiplexing method of claim 21 , the method further including comparing the intended byte alignment with the alignment in the snapshot data to determine if the two are the same.

23. The multiplexing method of claim 21 , the method further including serializing the byte aligned data and transmitting a serialized data signal to the second integrated circuit device.

24. A multiplexing system, the multiplexing system comprising:

a CMOS integrated circuit device, the CMOS integrated circuit device generating a plurality of 10 Gbit/Sec. serialized data signals;

a high speed integrated circuit device in electrical communication with the CMOS integrated circuit device, the high speed integrated circuit device including a multiplexer operable to generate a 40 Gbit/Sec. multiplexed output signal from the plurality of 10 Gbit/Sec. serialized data signals received from the CMOS integrated circuit; and

a phase data and byte snapshot back channel transmitted from the high speed integrated circuit device to the CMOS integrated circuit device, the phase data and byte snapshot back channel carrying phase information regarding bit alignment for each of the plurality of serialized data signals and periodic snapshots regarding byte alignment of the 10 Gbit/Sec. serialized data signals, the phase data and byte snapshot back channel being used by the CMOS integrated circuit device to adjust the phase of each of the plurality of 10 Gbit/Sec. serialized data signals to preserve bit and byte alignment.

25. The multiplexing system of claim 24 , wherein the high speed integrated circuit device is one of a bipolar and GaAs device.