Method of manufacturing a semiconductor integrated circuit and semiconductor integrated circuit
View Patent ↗Conventionally, when an electric potential of a supporting substrate is fixed, there arises a problem in that impact ions are generated even in the vicinity of embedded insulating film in the proximity of a drain due to generation of a parasitic transistor using the supporting substrate as a gate so as to be likely to cause a parasitic bipolar operation. A method of the present invention includes the steps of: forming and patterning a LOCOS reaching an embedded insulating film, a gate oxide film, a well and a polysilicon film serving as a gate electrode; forming a second conductivity type high-density impurity region in an ultra-shallow portion of each of a source region and a drain region, a second conductivity type impurity region having a low density under the second conductivity type high-density impurity region of the ultra-shallow portion, and a second conductivity type impurity region having a high density under the second conductivity type impurity region having a low density and above the embedded insulating film; forming a sidewall around the gate electrode; forming a second conductivity type impurity region in each of the source region and the drain region; forming an interlayer insulating film and forming contact holes in the source region, the drain region and the gate electrode; and forming a wiring on the interlayer insulating film.
1. A method of manufacturing a semiconductor integrated circuit, in circuit in which a CMOS transistor is formed on a first conductivity type semiconductor film provided on a first conductivity type supporting substrate through an embedded insulating film, comprising the steps of:
conducting thermal oxidation to form a LOCOS for element separation between transistors in the semiconductor film;
forming a gate oxide film of a first second conductivity type transistor;
forming a first conductivity type impurity region between the gate oxide film and the embedded insulating film in a region where the first second conductivity type transistor is to be formed;
forming a polysilicon film on the gate oxide film and etching the polysilicon film so as to form a gate electrode of the first second conductivity type transistor;
forming a second conductivity type impurity region in an ultra-shallow portion of each of a source region and a drain region;
forming a second conductivity type impurity region having a low density in a middle portion of each of the source region and the drain region;
forming a second conductivity type impurity region having the same density as the second conductivity type impurity region in the ultra-shallow portion in a lower portion of each of the source region and the drain region;
forming an insulating film on the source region, the drain region, and the gate electrode;
dry etching the insulating film formed on the source region, the drain region, and the gate electrode to form a sidewall around the gate electrode; and
performing ion implantation using the sidewall as a mask so as to form a second conductivity type impurity region in each of the source region and the drain region.