Attribute cache memory

1. A memory system, comprising:

a plurality of content addressable word decoders; and

memory cells associated with each of the word decoders,

wherein the memory cells are grouped into memory clusters,

each cluster being associated with one of the word decoders,

the word decoders being simultaneously addressable.

2. A memory system as recited in claim 1 , wherein the memory cells are random access memory.

3. A memory system as recited in claim 1 , wherein the memory cells are read only memory.

4. A memory system as recited in claim 1 , wherein a match of a subset of a memory address to a word stored in one of the word decoders causes the word decoder to select the associated memory cells.

5. A memory system as recited in claim 1 , wherein the word decoder has more than 16 address line inputs.

6. A memory system, comprising:

a plurality of content addressable word decoders; and

memory cells associated with each of the word decoders,

wherein a match of a subset of a memory address to a word stored in one of the word decoders causes the word decoder to select the associated memory cells,

wherein the subset of the memory address includes the most significant bits of the address.

7. A memory system, comprising:

a plurality of content addressable word decoders; and

memory cells associated with each of the word decoders,

wherein a match of a subset of a memory address to a word stored in one of the word decoders causes the word decoder to select the associated memory cells,

wherein the memory cells are grouped into memory clusters, wherein each memory cluster includes several memory word packets, each word packet comprising a plurality of memory cells, wherein another subset of the memory address is used to select one of the word packets of the selected memory cluster.

8. A memory system as recited in claim 7 , wherein the other subset of the memory address includes least significant bits of the address.

9. A memory system, comprising:

a plurality of content addressable word decoders; and

memory cells associated with each of the word decoders,

wherein a match of a subset of a memory address to a word stored in one of the word decoders causes the word decoder to select the associated memory cells,

wherein the memory address is an RF code associated with an object.

10. A memory system, comprising:

a plurality of content addressable word decoders; and

memory cells associated with each of the word decoders,

wherein a match of a subset of a memory address to a word stored in one of the word decoders causes the word decoder to select the associated memory cells,

wherein the memory address is an RF code associated with an RFID tag.

11. A memory system, comprising:

a plurality of content addressable word decoders; and

memory cells associated with each of the word decoders,

wherein the memory cells are grouped into memory clusters, wherein each memory cluster comprises multiple word packets, each word packet comprising a plurality of memory cells, wherein the word packets in a particular memory cluster contain data associated with a consecutive series of memory addresses.

12. A memory system, comprising:

a word decoder storing a modifiable identifier which is a subset of a memory address, the word decoder being responsive to a match of the identifier and an incoming subset of the memory address,

wherein memory cells are grouped into a memory cluster, the memory cluster being associated with the word decoder, wherein the memory cluster includes several memory word packets, each word packet comprising a plurality of memory cells, wherein another subset of the memory address is used to select one of the word packets of the memory cluster.

13. A memory system as recited in claim 12 , wherein a match of the identifier to the incoming subset of the memory address causes the word decoder to select an associated memory cell.

14. A memory system as recited in claim 12 , wherein memory cells are grouped into a memory cluster, the memory cluster being associated with the word decoder, wherein the memory cluster includes several memory word packets, each word packet comprising a plurality of memory cells, wherein another subset of the memory address is used to select one of the word packets of the memory cluster.

15. A memory system as recited in claim 12 , wherein the other subset of the memory address includes least significant bits of the address.

16. A memory system as recited in claim 12 , comprising:

a word decoder storing a modifiable identifier which is a subset of a memory address, the word decoder being responsive to a match of the identifier and an incoming subset of the memory address,

wherein the memory address is an RF code associated with an object.

17. A memory system, comprising:

a word decoder storing a modifiable identifier which is a subset of a memory address, the word decoder being responsive to a match of the identifier and an incoming subset of the memory address,

wherein the subset of the memory address includes most significant bits of the address.

18. A memory system, comprising

a word decoder storing a modifiable identifier which is a subset of a memory address, the word decoder being responsive to a match of the identifier and an incoming subset of the memory address,

a memory cluster associated with the word decoder, the memory cluster comprises multiple memory cells, wherein the memory cells in the memory cluster contain data associated with a consecutive series of memory addresses.

19. A memory system, comprising:

a word decoder array having fewer word decoders than combinations of word decoder addresses, the word decoders in the array being simultaneously addressable.

20. A memory system as recited in claim 19 , wherein each word decoder is responsive to a subset of one of the memory addresses.

21. A memory system, comprising:

a word decoder array having fewer word decoders than combinations of word decoder addresses; and

a memory cluster associated with each word decoder, each memory cluster comprises multiple memory cells, wherein the memory cells in a particular memory cluster contain data associated with a consecutive series of memory addresses.

22. A memory system, comprising:

a plurality of memory clusters, each of the memory clusters comprising a plurality of word packets, each word packet comprising a plurality of bits;

a plurality of first addressing mechanisms for selecting a particular one of the clusters; and

a second addressing mechanism for selecting one of the word packets in a selected one of the clusters.

23. A memory system as recited in claim 22 , wherein the first addressing mechanisms are responsive to a first subset of a memory address, wherein the second addressing mechanisms are responsive to a second subset of the memory address.

24. A memory system as recited in claim 22 , wherein the memory cells in a particular memory cluster contain data associated with a consecutive series of memory addresses.

25. A method for providing access to kill codes, comprising:

identifying an identification number of an RE tag;

matching at least a portion of the identification number to a stored memory address;

accessing a word packet associated with the memory address; and

retrieving a kill code from the word packet.

26. A method as recited in claim 25 , wherein the word packet comprises multiple memory cells, and further comprising using at least a portion of the identification number to select one of the memory clusters.

27. A method as recited in claim 25 , wherein the word packet comprises multiple memory cells, wherein the word packets contain kill code associated with a consecutive series of identification numbers.

28. A memory system comprised of a plurality of memory clusters, each memory cluster including a plurality of word packets, each word packet including a plurality of memory cells, wherein the word packets in a particular memory cluster contain data associated with a consecutive series of memory addresses.

29. A memory system, comprising

a memory cluster, each memory cluster comprising a plurality of memory cells;

a word decoder; and

a mechanism for simultaneously modifying contents of at least two of the clusters based on information stored in the word decoders.

30. A memory system, comprising:

a plurality of word decoders;

a mechanism for physical access to individual word decoders; and

a mechanism for accessing individual word decoders via a content addressable memory associated therewith.