IP Library Granted Patent US 7,342,212
Granted Patent B2
US 7,342,212 · App. 11/395,193 · Granted Mar 11, 2008

Analog vertical sub-sampling in an active pixel sensor (APS) image sensor

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Quick Facts
Patent No.
US 7,342,212
App. No.
11/395,193
Granted
Mar 11, 2008
Kind
B2
Abstract

An active pixel sensor (APS) image sensor comprises an array of pixel circuits corresponding to rows and columns of pixels, a plurality of amplifiers that buffer signals output by the array of pixel circuits, and a plurality of sample and hold circuits that read the buffered signals. A routing mechanism is positioned between the array of pixel circuits and the plurality of amplifiers. A controller selects a set of the pixel circuits for sampling and is configured to control the routing mechanism to couple each pixel circuit in the set to a different one of the amplifiers during a normal mode of operation and to couple each pixel circuit of a subset of pixel circuits in a first set of pixel circuits to a different amplifier of a first subset of the amplifiers, to couple each pixel circuit of a subset of pixel circuits in a second set of pixel circuits to a different amplifier of a second subset of the amplifiers, and to connect the amplifiers of the first and second subsets of amplifiers in pairs to a common one of the sample and hold circuits during a sub-sampling mode of operation.

Claims (41)

1. An active pixel sensor (APS) image sensor comprising:

an array of pixel circuits corresponding to rows and columns of pixels;

a plurality of amplifiers that buffer signals output by the array of pixel circuits;

a plurality of sample and hold circuits that read the buffered signals;

a routing mechanism positioned between the array of pixel circuits and the plurality of amplifiers; and

a controller that selects sets of pixels circuits for sampling, the controller configured to control the routing mechanism (1) to couple each pixel circuit in a set to a different one of the amplifiers during a normal mode of operation, and (2) to couple respective pixel circuits of a first row of pixel circuits in a first set of pixel circuits to respectively different amplifiers of a first subset of the amplifiers, to couple respective pixel circuits of a second row of pixel circuits in a second set of pixel circuits to respectively different amplifiers of a second subset of the amplifiers during a sub-sampling mode, and the controller further configured to control coupling of the amplifiers of the first and second subsets of amplifiers in pairs to a common one of the sample and hold circuits during the sub-sampling mode of operation.

2. The image sensor of claim 1 , wherein the pixel circuits of each of the first and second rows of the pixel circuits are in nonadjacent columns.

3. The image sensor of claim 1 , wherein the first and second rows of pixel circuits are nonadjacent.

4. The image sensor of claim 3 , wherein the pixel circuits of each of the first and second rows of the pixel circuits are in nonadjacent columns.

5. The image sensor of claim 1 , wherein the plurality of amplifiers include an amplifier associated with each column of pixel circuits.

6. The image sensor of claim 1 , wherein the controller is configured to control the routing mechanism to connect each pair of the amplifiers to the common sample and hold amplifier for simultaneous reading.

7. The image sensor of claim 1 , wherein each of the pixel circuits is associated with one of a plurality of different colors and wherein the pixel circuits of the first row of pixel circuits of the first set of pixel circuits and the pixel circuits of the second row of pixel circuits of the second set of pixel circuits are all associated with a common color.

8. An integrated circuit including an active pixel sensor (APS) image sensor comprising:

an array of pixel circuits corresponding to rows and columns of pixels;

a plurality of amplifiers that buffer signals output by the array of pixel circuits, each column of pixel circuits of the array of pixel circuits having an associated amplifier;

a plurality of sample and hold circuits that read the buffered signals; a routing mechanism positioned between the array of pixel circuits and the plurality of amplifiers such that (1) in a first mode of operation the routing mechanism routes signals output by each column of the pixel circuits to the amplifier associated with the column of respective pixel circuits and (2) in a second mode of operation the routing mechanism selectively routes the signals output by a subset of columns of the pixel circuits to the amplifier associated with the column of the respective pixel circuits and a corresponding amplifier not associated with the subset of columns, each amplifier associated with the column of the respective pixel circuits and the corresponding amplifier thereof defining a respective pair of a plurality of pairs of amplifiers; and

a controller for selecting the first or second mode of operation for sampling, wherein each sample and hold circuit of the plurality of sample and hold circuits, during the second mode of operation, samples a respective pair of amplifiers.

9. The integrated circuit of claim 8 , wherein

the controller selects first and second sets of pixels circuits for sampling,

the first set of pixel circuits is a first row of pixel circuits, and the second set of pixel circuits is a second row of pixel circuits, and

the controller is configured to control the routine mechanism to selectively couple each pixel circuit in the first set and second set to one of (1) the amplifier associated with the column of the respective pixel circuit, or (2) the amplifier associated with the column of the respective pixel circuit and the corresponding amplifier, respectively.

10. The integrated circuit of claim 9 , wherein the subset of columns of the pixel circuits are nonadjacent columns.

11. The integrated circuit of claim 9 , wherein the first and second rows of pixel circuits are nonadjacent.

12. The integrated circuit of claim 11 , wherein the subset of columns of the pixel circuits are nonadjacent columns.

13. The integrated circuit of claim 8 , wherein the controller is configured to control the routing mechanism to connect each pair of the amplifiers to the common sample and hold amplifier for simultaneous reading.

14. The integrated circuit of claim 9 , wherein each of the pixel circuits is associated with one of a plurality of different colors and wherein the pixel circuits of a subset of pixel circuits of the first set of pixel circuits and the pixel circuits of a subset of pixel circuits of the second set of pixel circuits are all associated with a common color.

15. A method of operating an active pixel sensor (APS) image sensor that includes an array of pixel circuits arranged in rows and columns, a plurality of amplifiers that buffer signals output by the array of pixel circuits, and a plurality of sample and hold circuits that read the buffered signals, each column of pixel circuits of the array of pixel circuits having an associated amplifier of the plurality of amplifiers; the method comprising:

selecting, using a controller, a first mode of operation or a second mode of operation;

responsive to the selecting of the first mode of operation, routing, by the routing mechanism, signals output by each column of the pixel circuits to an amplifier associated with the column of respective pixel circuits;

responsive to the selecting of the second mode of operation, alternately routing, by the routing mechanism, signals output by respective nonadjacent columns of the pixel circuits to the amplifier associated with the column of the respective pixel circuits and a corresponding amplifier which corresponds to the amplifier associated with the column of the respective pixel circuits and is not associated with the respective nonadjacent columns;

simultaneously reading from each sample and hold circuit a pair of the amplifier associated with a respective column and the corresponding amplifier during the second mode of operation.

16. The method of claim 15 , wherein a first set of pixel circuits is a first row of pixel circuits and a second set of pixel circuits is a second row of pixel circuits, the method including:

controlling the routing mechanism to selectively couple each pixel circuit in the first set and second set to one of (1) the amplifier associated with the column of the respective pixel circuits, or (2) the amplifier associated with the column of the respective pixel circuits and the corresponding amplifier, respectively.

17. The method of claim 16 , wherein the first and second rows of pixel circuits are nonadjacent.

18. The method of claim 15 wherein the first and second rows of pixel circuits include subsets of pixel circuits and the pixel circuits of each of the subsets of pixel circuits are in nonadjacent columns.

19. An active pixel sensor (APS) image sensor comprising:

an array of pixel circuits corresponding to rows and columns of pixels;

a plurality of amplifiers positioned between the plurality of sample and hold circuits and the array of pixel circuits for receiving and buffering signals output by the array of pixel circuits, each column of pixel circuits of the array of pixel circuits having an associated amplifier of the plurality of amplifiers;

a plurality of sample and hold circuits for reading the buffered signals;

a routing mechanism positioned between the array of pixel circuits and the plurality of amplifiers to alternately route the signals output by respective nonadjacent columns of the pixel circuits to the amplifier associated with the column of the respective pixel circuits and a corresponding amplifier which is not associated with the respective nonadjacent columns,

wherein each amplifier associated with the column of the respective pixel circuits and the corresponding amplifier thereof defines a respective pair of a plurality of pairs of amplifiers, and each sample and hold circuit of the plurality of sample and hold circuits samples a respective pair of amplifiers such that values from pixel circuits in each respective non-adjacent column are sub-sampled.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 14, 2016
From: AVAGO TECHNOLOGIES IMAGING IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES SENSOR IP PTE. LTD.
Reel/Frame 040357/0614 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 13, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES IMAGING IP (SINGAPORE) PTE. LTD.
Reel/Frame 040350/0903 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 30, 2010
From: MICRON TECHNOLOGY, INC.
To: APTINA IMAGING CORPORATION
Reel/Frame 024160/0051 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 7, 2007
From: AVAGO TECHNOLOGIES IMAGING HOLDING CORPORATION
To: MICRON TECHNOLOGY, INC.
Reel/Frame 019407/0441 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 3, 2007
From: AVAGO TECHNOLOGIES IMAGING HOLDING CORPORATION
To: MICRON TECHNOLOGY, INC.
Reel/Frame 018757/0159 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 21, 2006
From: MENTZER, RAY ALLEN; DEMONTE, FRANK J.; BECK, JEFFERY STEVEN; BORG, MATTHEW MICHAEL; MYERS, CHARLES GRANT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 018151/0040 →