Method for implementing error-correction codes in flash memory
The present invention teaches a method and device for implementing error-correction code (ECC) in flash memory. The present invention discloses methods which utilize a modified ECC algorithm, and a flash memory device which incorporates these methods.
1. A method for storing a plurality of data bits into a flash memory device, the method comprising:
providing an error-correction code to generate at least one parity bit from a plurality of data bits;
transforming a plurality of data bits to be stored in the flash memory device, thereby generating a plurality of transformed data bits;
applying said error-correction code to said plurality of transformed data bits, thereby generating at least one parity bit;
transforming said at least one parity bit, thereby generating at least one transformed parity bit, wherein said at least one transformed parity bit is a complement of said at least one parity bit; and
storing the plurality of data bits and said at least one transformed parity bit in the flash memory device, wherein an all-one group of bits is stored for at least one value of the plurality of data bits.
2. The method of claim 1 , wherein said step of applying said error-correction code to said plurality of transformed data bits does not generate an all-one codeword for any value of the data bits.
3. The method of claim 1 , wherein said step of transforming the data bits, thereby generating said plurality of transformed data bits, includes generating complements of the data bits.
4. A flash memory device comprising:
an error-correction code module configured to generate at least one parity bit from a plurality of data bits; and
a flash memory controller configured to:
transform the plurality of data bits to generate a plurality of transformed data bits;
transform said at least one parity bit to generate at least one transformed parity bit, wherein said at least one transformed parity bit is a complement of said at least one parity bit; and
store said plurality of data bits and said at least one transformed parity bit in the flash memory device, wherein an all-one group of bits is stored for at least one value of the plurality of data bits.
5. The device of claim 4 , wherein said error-correction code module is included in said flash memory controller.
6. The device of claim 4 , wherein said error-correction code module is included in a host system.
7. The device of claim 4 , wherein a codeword generated by said error-correction code module from said plurality of data bits is not an all-one codeword for any value of the plurality of data bits.
8. The device of claim 4 , wherein said plurality of transformed data bits is a plurality of complements of the plurality of data bits.
9. The method of claim 1 , further comprising storing the plurality of transformed data bits within the flash memory device.
10. The method of claim 1 , further comprising detecting a data error using the plurality of transformed data bits and the at least one transformed parity bit.
11. The method of claim 1 , further comprising indicating an operational error where power to the flash memory device is interrupted during an erasure procedure.
12. The method of claim 1 , further comprising providing the error-correction code at the flash memory device.
13. The method of claim 1 , further comprising providing the error-correction code at a host device coupled to the flash memory device.
14. The method of claim 1 , wherein the error-correction code includes a linear systematic code.
15. The method of claim 1 , further comprising transferring the plurality of data bits to the flash memory device from a host coupled to the flash memory device.
16. The device of claim 4 , wherein the flash memory controller is further configured to transfer the plurality of transformed bits to the error-correction code module.
17. A computing system, comprising:
a host device; and
a flash memory device coupled to the host device and comprising:
an error-correction code module configured to generate at least one parity bit from a plurality of data bits; and
a flash memory controller configured to:
transform data bits to generate a plurality of transformed data bits;
transform the at least one parity bit to generate at least one transformed parity bit, wherein the at least one transformed parity bit is a complement of the at least one parity bit; and
store the plurality of data bits and the at least one transformed parity bit in the flash memory device, wherein an all-one group of bits is stored for at least one value of the plurality of data bits.
18. The computing system of claim 17 , wherein a codeword generated by the error-correction code module from the plurality of data bits is not an all-one codeword for any value of the plurality of data bits.
19. The device of claim 4 , wherein a codeword generated by the error-correction code module from the plurality of data bits is a legal codeword.
20. The device of claim 4 , wherein the plurality of data bits includes an erased page.