IP Library Granted Patent US 7,321,252
Granted Patent B2
US 7,321,252 · App. 11/396,543 · Granted Jan 22, 2008

Semiconductor integrated circuit

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Quick Facts
Patent No.
US 7,321,252
App. No.
11/396,543
Granted
Jan 22, 2008
Kind
B2
Abstract

In order to provide a semiconductor IC unit such as a microprocessor, etc., which satisfies both fast operation and lower power consumption properties with its high quality kept, the semiconductor IC unit of the present invention is composed so as to include a main circuit (LOG) provided with transistors, which is formed on a semiconductor substrate, and a substrate bias controlling circuit (VBC) used for controlling a voltage to be applied to the substrate, and the main circuit includes switching transistors (MN 1 and MP 1 ) used for controlling a voltage to be applied to the substrate and control signals output from the substrate bias controlling circuit is entered to the gate of each of the switching transistors and the control signal is returned to the substrate bias controlling circuit.

Claims (22)

1. A semiconductor integrated circuit device comprising:

an I/O circuit; and

a logic circuit comprising at least one first MOSFET of a first conductivity type on a first well area of a second conductivity type;

wherein the I/O circuit input and output signals to and from the semiconductor integrated circuit device are via a terminal PAD;

wherein the I/O circuit comprises a level converter used to convert a second voltage amplitude to a first voltage amplitude;

wherein at least one second MOSFET between the level converter and the terminal pad in the I/O circuit is driven by the first voltage;

wherein the first voltage is supplied to the first well area as substrate voltage and the second voltage is supplied to the first MOSFET as operation voltage while the logic circuit is in standby state; and

wherein the absolute value of the first voltage is higher than that of the second voltage.

2. The semiconductor integrated circuit device of claim 1 ,

wherein the logic circuit further comprises at least one third MOSFET of second conductivity type on a second well area of first conductivity type.

3. The semiconductor integrated circuit device of claim 1 ,

wherein the second voltage is supplied to the first well area as the substrate voltage in active state.

4. The semiconductor integrated circuit device of claim 1 ,

wherein the first conductivity type is p-type; and

wherein the second conductivity type is n-type.

5. The semiconductor integrated circuit device of claim 1 ,

wherein the thickness of the oxide film of the second MOSFET between the level converter and the terminal pad is thicker than that of the first MOSFET of the logic circuit.

6. The semiconductor integrated circuit device of claim 1 ,

wherein the absolute value of the threshold voltage of the second MOSFET is larger than that of the first MOSFET.

7. The semiconductor integrated circuit device of claim 3 ,

wherein the logic circuit requires a fast operation in the active state; and

wherein the logic circuit does not require fast operation in the standby state.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 053654 FRAME: 0254. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jun 10, 2021
From: STARBOARD VALUE INTERMEDIATE FUND LP
To: ACACIA RESEARCH GROUP LLC
Reel/Frame 057454/0045 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR NAME PREVIOUSLY RECORDED ON REEL 052853 FRAME 0153. ASSIGNOR(S) HEREBY CONFIRMS THE PATENT SECURITY AGREEMENT. Recorded Mar 2, 2021
From: ACACIA RESEARCH GROUP LLC
To: STARBOARD VALUE INTERMEDIATE FUND LP, AS COLLATERAL AGENT
Reel/Frame 056775/0066 →
RELEASE OF SECURITY INTEREST IN PATENTS Recorded Jul 8, 2020
From: STARBOARD VALUE INTERMEDIATE FUND LP
To: ACACIA RESEARCH GROUP LLC; AMERICAN VEHICULAR SCIENCES LLC; BONUTTI SKELETAL INNOVATIONS LLC; CELLULAR COMMUNICATIONS EQUIPMENT LLC; INNOVATIVE DISPLAY TECHNOLOGIES LLC; LIFEPORT SCIENCES LLC; LIMESTONE MEMORY SYSTEMS LLC; MOBILE ENHANCEMENT SOLUTIONS LLC; MONARCH NETWORKING SOLUTIONS LLC; NEXUS DISPLAY TECHNOLOGIES LLC; PARTHENON UNIFIED MEMORY ARCHITECTURE LLC; R2 SOLUTIONS LLC; SAINT LAWRENCE COMMUNICATIONS LLC; STINGRAY IP SOLUTIONS LLC; SUPER INTERCONNECT TECHNOLOGIES LLC; TELECONFERENCE SYSTEMS LLC; UNIFICATION TECHNOLOGIES LLC
Reel/Frame 053654/0254 →
PATENT SECURITY AGREEMENT Recorded Jun 5, 2020
From: ACACIA RESEARCH GROUP LLC; AMERICAN VEHICULAR SCIENCES LLC; BONUTTI SKELETAL INNOVATIONS LLC; CELLULAR COMMUNICATIONS EQUIPMENT LLC; INNOVATIVE DISPLAY TECHNOLOGIES LLC; LIFEPORT SCIENCES LLC; LIMESTONE MEMORY SYSTEMS LLC; MERTON ACQUISITION HOLDCO LLC; MOBILE ENHANCEMENT SOLUTIONS LLC; MONARCH NETWORKING SOLUTIONS LLC; NEXUS DISPLAY TECHNOLOGIES LLC; PARTHENON UNIFIED MEMORY ARCHITECTURE LLC; R2 SOLUTIONS LLC; SAINT LAWRENCE COMMUNICATIONS LLC; STINGRAY IP SOLUTIONS LLC; SUPER INTERCONNECT TECHNOLOGIES LLC; TELECONFERENCE SYSTEMS LLC; UNIFICATION TECHNOLOGIES LLC
To: STARBOARD VALUE INTERMEDIATE FUND LP, AS COLLATERAL AGENT
Reel/Frame 052853/0153 →
MERGER Recorded Aug 26, 2010
From: RENESAS TECHNOLOGY CORP.
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 024892/0272 →