Surface passivation of GaN devices in epitaxial growth chamber
View Patent ↗The present invention relates to passivation of a gallium nitride (GaN) structure before the GaN structure is removed from an epitaxial growth chamber. The GaN structure includes one or more structural epitaxial layers deposited on a substrate, and the passivation layer deposited on the structural epitaxial layers. In general, the passivation layer is a dielectric material deposited on the GaN structure that serves to passivate surface traps on the surface of the structural epitaxial layers. Preferably, the passivation layer is a dense, thermally deposited silicon nitride passivation layer.
1. A gallium nitride (GaN) epitaxial structure manufactured in a growth chamber by a process comprising:
a) depositing one or more structural epitaxial layers on a substrate, the one or more structural epitaxial layers including a GaN buffer layer in the growth chamber; and
b) depositing a passivation layer on the one or more structural epitaxial layers, thereby forming a GaN structure that is passivated before the GaN structure is removed from the growth chamber, wherein the passivation layer comprises a pyrolitic silicon nitride.
2. The structure of claim 1 wherein the passivation layer is a thermally assisted silicon nitride passivation layer.
3. The structure of claim 1 wherein the process further comprises:
a) forming a source contact on the one or more structural epitaxial layers in an etched source region of the passivation layer;
b) forming a gate contact on the one or more structural epitaxial layers in an etched gate region of the passivation layer; and
c) forming a drain contact on the one or more structural epitaxial layers in an etched drain region of the passivation layer,
thereby forming a high electron mobility transistor.
4. The structure of claim 1 wherein the process further comprises:
a) forming a source contact on the one or more structural epitaxial layers in an etched source region of the passivation layer;
b) forming a gate contact on the passivation layer; and
c) forming a drain contact on the one or more structural epitaxial layers in an etched drain region of the passivation layer,
thereby forming a metal-insulator-semiconductor field effect transistor.
5. The structure of claim 1 wherein the passivation layer is deposited using pyrolysis.
6. The structure of claim 1 wherein the depositing the one or more structural epitaxial layers comprises depositing a transitional layer on the substrate.
7. The structure of claim 6 wherein the depositing the one or more structural epitaxial layers further comprises depositing the GaN buffer layer on the transitional layer.
8. The structure of claim 7 wherein the depositing the one or more structural epitaxial layers further comprises depositing an aluminum gallium nitride (AlGaN) Schottky layer on the GaN buffer layer.
9. The structure of claim 8 wherein the depositing the one or more structural epitaxial layers further comprises depositing a GaN termination layer on the AlGaN Schottky layer.
10. The structure of claim 6 wherein the depositing the one or more structural epitaxial layers further comprises depositing a sub-buffer layer on the transitional layer.
11. The structure of claim 10 wherein the sub-buffer layer is essentially aluminum nitride.
12. The structure of claim 10 wherein the depositing the one or more structural epitaxial layers further comprises depositing the GaN buffer layer on the sub-buffer layer.
13. The structure of claim 12 wherein the depositing the one or more structural epitaxial layers further comprises depositing a aluminum gallium nitride (AlGaN) Schottky layer on the GaN buffer layer.
14. The structure of claim 13 wherein the depositing the one or more structural epitaxial layers further comprises depositing a GaN termination layer on the AlGaN Schottky layer.