Semiconductor device and method of manufacturing the same
View Patent ↗A semiconductor device has a semiconductor substrate and a high-resistance first conductivity type well region disposed on the semiconductor substrate. A low-resistance second conductivity type source region and a low-resistance second conductivity type drain region are formed in the well region. The well region is formed with trenches having convex and concave portions and that are disposed parallel to a source-drain direction of the source and drain regions. A gate insulating film is disposed on surfaces of the convex and concave portions of the trenches. A gate electrode is disposed on the gate insulating film.
1. A semiconductor device comprising:
a semiconductor substrate;
a high-resistance first conductivity type well region disposed on the semiconductor substrate;
a low-resistance second conductivity type source region and a low-resistance second conductivity type drain region formed in the well region;
a plurality of trenches formed in the well region and disposed parallel to a source-drain direction of the source and drain regions, the trenches having convex and concave portions;
a gate insulating film disposed on surfaces of the convex and concave portions of the trenches; and
a gate electrode disposed on the gate insulating film.
2. A semiconductor device according to claim 1 ; wherein the source region and the drain region are formed in the vicinity of portions of the trenches at opposite ends thereof.
3. A semiconductor device according to claim 1 ; wherein the gate electrode extends across the convex and concave portions of the trenches.
4. A semiconductor device comprising:
a semiconductor substrate;
a well region disposed on the semiconductor substrate;
a source region and a drain region formed in the well region;
a plurality of trenches formed in the well region and disposed parallel to a source-drain direction corresponding to the source region and the drain region;
a gate insulating film disposed on surfaces of the trenches; and
a gate electrode film disposed over the semiconductor substrate, the gate electrode film having a portion extending into the trenches and a surface portion disposed outside of the trenches and extending in a direction away from the semiconductor substrate.
5. A semiconductor device according to claim 4 ; wherein the well region comprises a high-resistance first conductivity type well region; and wherein the source and drain regions comprise low-resistance second conductivity type source and drain regions.
6. A semiconductor device according to claim 4 ; wherein the well region has a first surface disposed on the semiconductor substrate and a second surface opposite to the first surface; and wherein the trenches extend only up to a central portion of the well region from the second surface thereof.
7. A semiconductor device according to claim 4 ; wherein the trenches form a plurality of convex and concave portions; and wherein the gate insulating film is disposed on surfaces of the concave and convex portions of the trenches.
8. A semiconductor device according to claim 4 ; wherein the trenches form a plurality of convex and concave portions; and wherein the gate electrode film extends at least partly across the convex and concave portions of the trenches.
9. A semiconductor device according to claim 4 ; wherein the trenches extend between the source region and the drain region.
10. A semiconductor device according to claim 4 ; wherein the semiconductor device has a double diffusion drain (DDD) structure.
11. A semiconductor device according to claim 4 ; wherein the semiconductor device has a lateral double diffused MOS (LDMOS) structure.
12. A semiconductor device according to claim 4 ; wherein the trenches form a plurality of convex and concave portions, each of the convex portions having a width of approximately 1,000 Å.
13. A semiconductor device according to claim 4 ; wherein the semiconductor device has a twin-well construction.
14. A semiconductor device comprising:
a semiconductor substrate;
a well region having a first conductivity type of high resistance and disposed at a given preselected depth from a surface of the semiconductor substrate;
a plurality of trenches forming a plurality of convex and concave portions, each of the trenches extending from a surface of the well region to approximately a center of the preselected depth;
a gate insulating film disposed on surfaces of the convex and concave portions of the plurality of trenches;
a gate electrode film having a portion embedded into the plurality of trenches and a surface portion disposed on the semiconductor substrate, the gate electrode film extending across the convex and concave portions of the plurality of trenches except for a portion of the gate electrode film in a vicinity of opposite ends of the plurality of trenches; and
a source region and a drain region each having a second conductivity of low resistance and being disposed in the well region, the plurality of trenches extending parallel to a source-drain direction.
15. A semiconductor device according to claim 14 ; wherein the semiconductor device has a double diffusion drain (DDD) structure.
16. A semiconductor device according to claim 14 ; wherein the semiconductor device has a lateral double diffused MOS (LDMOS) structure.
17. A semiconductor device according to claim 14 ; wherein each of the convex portions of the plurality of trenches has a width of approximately 1,000 Å.
18. A semiconductor device according to claim 14 ; wherein an inner portion of each of the convex portions of the plurality of trenches has a width so as to become fully depleted in an ON state of the semiconductor device.
19. A semiconductor device according to claim 14 ; wherein the semiconductor device has a twin-well construction.
20. A semiconductor device according to claim 14 ; wherein the first and second conductivity types are inverted conductivity types.