Thin film transistor including organic semiconductor layer and substrate including the same
View Patent ↗Provided is a thin film transistor including a gate electrode on a substrate; a gate insulating layer on the gate electrode; source and drain electrodes including first source and drain layers on the gate insulating layer, respectively, and spaced apart from each other, wherein at lease one of the first source and drain layers includes indium-tin-oxide doped with at least one Group III element; and an organic semiconductor layer on the gate insulating layer and contacting the first source and drain layers.
1. A method of fabricating an array substrate, comprising:
forming a gate electrode on a substrate;
forming a gate insulating layer on the gate electrode;
forming source and drain electrodes comprising first source and drain layers on the gate insulating layer, respectively, and second source and drain layers on the source and drain layers, respectively, and spaced apart from each other, wherein at least one of the second source and drain layers comprises indium-tin-oxide doped with at least one Group III element;
forming an organic semiconductor layer on the gate insulating layer and contacting the second source and drain layers; and
forming a data line connected to the source electrode,
wherein the at least one Group III element includes boron (B),
wherein the first source and drain layers have a resistance lower than a resistance of the second source and drain layers,
wherein the second source and drain layers fully cover the first source and drain layers, respectively,
wherein a top surface of the gate insulating layer is even, whereby the source and drain electrodes and the data line directly on the gate insulating layer are even,
wherein the data line consists of a layer made of the same material as the first source and drain layers, and
wherein a heat-treating step is conducted prior to forming the organic semiconductor layer such that surfaces of the second source and drain layers are smoothed, and a temperature of the heat-treating is equal to or less than 200 degrees centigrade.
2. The method according to claim 1 , wherein said second source and drain layers both comprise indium-tin-oxide doped with at least one Group III element.
3. The method according to claim 1 , wherein the data line, the first source layer and the first drain layer are formed in the same step.
4. The method according to claim 1 , further comprising forming a. passivation layer having an drain contact hole exposing a part of the drain electrode and forming a pixel electrode contacting the part of the drain electrode through the drain contact hole.
5. The method according to claim 1 , wherein the substrate comprises a glass substrate or a plastic substrate.
6. The method according to claim 1 , wherein all steps of fabricating the array substrate are performed at equal to or less than 200 degrees centigrade.