Method, system and computer-readable code for testing of flash memory
View Patent ↗Methods, systems and devices for testing flash memory dies are disclosed. According to some embodiments, during the post-wafer sort stage of device manufacture, a plurality of flash memory devices, each of which includes a flash controller die and at least one flash memory die associated with a common housing, are subjected to a testing process, for examples, a batch testing process or a mass testing process. During testing, a respective flash controller residing on a respective flash controller die executes at least one test program to test one or more respective flash memory dies of the respective flash device. A testing system including at least 100 of the flash memory devices and a mass-testing board is disclosed. Furthermore, flash memory devices where the flash controller is operative to test one or more of the flash memory dies are disclosed. Exemplary testing includes but is not limited to bad block testing.
1. A method of device manufacturing comprising:
a) fabricating a plurality of flash memory devices, each said flash memory device including:
(i) a respective flash memory residing on at least one respective flash memory die and
(ii) a respective flash controller residing on a flash controller die separate from said respective at least one flash memory die, said respective at least one flash memory die and said respective flash controller die residing within, residing on, or attached to a common housing,
b) subjecting said plurality of fabricated flash memory devices to a testing process wherein a testing board is coupled to each of said plurality of fabricated flash memory devices and wherein each said flash memory controller executes at least one test program to test at least one respective said flash memory die while the flash memory device including said flash memory die is coupled to the test board.
2. The method of claim 1 wherein said testing process is a mass testing process.
3. The method of claim 2 wherein said subjecting of said flash memory devices to said mass testing process includes coupling said plurality of flash memory devices to a single testing board, and using said testing board to deliver electrical power to said plurality of flash memory devices.
4. The method of claim 1 further comprising: c) subsequent to said testing process, selling said plurality of flash memory devices as original equipment.
5. The method of claim 4 wherein each said flash memory device is fabricated as a respective multi-chip package.
6. The method of claim 4 wherein each said flash memory device is fabricated as a respective memory card.
7. The method of claim 1 wherein each of said flash memory controller and flash memory is provided within a common respective multi-chip packaging.
8. The method of claim 1 wherein each said flash memory of a respective said flash memory device comprises a plurality of flash memory dies, and each respective said flash controller tests a respective said plurality of flash memory dies by executing said at least one test program.
9. The method of claim 1 wherein for each said flash memory device, a respective said flash controller and a respective said at least one flash memory die are provided on a respective common printed circuit board.
10. The method of claim 1 wherein for each said flash memory device, at least one said test program resides at least in part within non-volatile memory of a respective said flash controller.
11. The method of claim 1 wherein for each said flash memory device, said test program resides at least in part within said respective flash memory.
12. The method of claim 1 wherein at least one said test program executed by each said flash controller identifies bad blocks in said respective flash memory.
13. The method of claim 1 wherein at least one said test program executed by each said flash controller affects bad block testing of a majority of memory cells of a respective said flash memory.
14. The method of claim 1 wherein at least one said test program executed by each said flash controller affects bad block testing of substantially all memory cells of a respective said flash memory.
15. The method of claim 1 wherein at least one said test program executed by each said flash controller tests memory cells of a respective said flash memory in a multi bit per cell mode.
16. The method of claim 1 wherein said execution of said at least one test program includes:
performing an error correction;
i) determining if the error correction was successful during a flash memory operation; and
ii) in the event that said determining indicates an error correction failure, recording a test failure.
17. A testing system comprising:
a) a plurality of at least 100 flash memory devices, each said flash memory device including a respective flash memory residing on a respective at least one flash memory die and a respective flash controller residing on a respective flash controller die separate from said respective at least one flash memory die, said respective at least one flash memory die and said respective flash controller die residing within, residing on, or attached to a common housing, each said flash memory controller operative to execute at least one test program to test a respective at least one said flash memory die; and
b) a mass-testing board having at least 100 ports configured to supply electrical power to said flash memory devices such that each said port supplies electrical power to a respective said flash memory device.
18. The system of claim 17 wherein at least one said test program executed by each said flash controller is operative to affect bad block testing of a majority of memory cells of a respective said flash memory.
19. The system of claim 17 wherein at least one said test program executed by each said flash controller is operative to affect bad block testing of substantially all memory cells of a respective said flash memory.
20. The system of claim 17 wherein the system is operative to test said plurality of at least 100 flash memory devices substantially simultaneously.
21. The system of claim 17 wherein each said flash memory controller is operative to execute at least one test program to test a respective at least one said flash memory die while the flash memory device including the flash memory die is coupled to the mass-testing board.