Global closed loop control system with DV/DT control and EMI/switching loss reduction
View Patent ↗A gate driver for a power switch, comprising a gate drive circuit coupled to the gate of the power switch for at least one of turning on and turning off the power switch; a gate voltage control circuit in the gate drive circuit for controlling a voltage applied to the gate of the power switch during at least one of turning on and turning off the power switch; and a signal supplied to the gate voltage control circuit indicative of a voltage rate of change per unit time to be applied in at least one of turning on and turning off the power switch.
1. A gate driver for a power switch, comprising:
a gate drive circuit coupled to the gate of the power switch for at least one of turning on and turning off the power switch;
a gate voltage control circuit in the gate drive circuit for controlling a voltage applied to the gate of the power switch during at least one of turning on and turning off the power switch;
a signal supplied to the gate voltage control circuit indicative of a voltage rate of change per unit time to be applied in at least one of turning on and turning off the power switch;
a level shifting circuit for shifting a reference for the gate driver to a high voltage reference; and
a variable pulse width generator coupled to the level shifting circuit and operable to provide the level shifting circuit with pulses indicative of a beginning and end of a gate command for the power switch; and
the pulses having a width that varies dependent upon a desired dv/dt control parameter.
2. A gate driver for a power switch, comprising:
a gate drive circuit coupled to the gate of the power switch for at least one of turning on and turning off the power switch;
a gate voltage control circuit in the gate drive circuit for controlling a voltage applied to the gate of the power switch during at least one of turning on and turning off the power switch;
a signal supplied to the gate voltage control circuit indicative of a voltage rate of change per unit time to be applied in at least one of turning on and turning off the power switch;
a level shifting circuit for shifting a reference for the gate driver to a high voltage reference; and
a pulse consolidation circuit for producing a switch command based on a beginning and end pulse, the switch command being applied to control the gate of the power switch.
3. The gate driver according to claim 2 , wherein the pulse consolidation circuit is an RS flip flop, with the beginning and end pulses coupled to inputs of the flip flop.
4. A gate driver for a power switch, comprising:
a gate drive circuit coupled to the gate of the power switch for at least one of turning on and turning off the power switch;
a gate voltage control circuit in the gate drive circuit for controlling a voltage applied to the gate of the power switch during at least one of turning on and turning off the power switch;
a signal supplied to the gate voltage control circuit indicative of a voltage rate of change per unit time to be applied in at least one of turning on and turning off the power switch;
a level shifting circuit for shifting a reference for the gate driver to a high voltage reference; and
a pulse to voltage converter coupled to the level shifting circuit and operable to provide an analog voltage level based on a width of an input pulse, the analog voltage level being applied to the gate voltage control circuit.