Electrical encoding of cable types and configurations

1. A system, comprising:

a first circuit assembly having a plurality of circuit traces;

a second circuit assembly having a plurality of circuit traces;

a cable assembly connecting the plurality of circuit traces on the first circuit assembly to the plurality of circuit traces on the second circuit assembly;

signal generating circuitry to generate signal values on one or more of the plurality of circuit traces in the first circuit assembly; and

an operational logic module to compare signal values on one or more of the plurality of circuit traces in the second circuit assembly to an expected signal value.

2. The system of claim 1 , wherein the signal generating circuitry to generate signal values on one or more of the plurality of circuit traces in the first circuit assembly comprises one or more bias voltage devices connected to one or more of the plurality of circuit traces.

3. The system of claim 1 , wherein the an operational logic module comprises:

logic to detect a signal level on one or more of the plurality of circuit traces in the second circuit assembly; and

logic to compare the signal level to a reference signal level stored in a memory location.

4. The system of claim 3 , wherein the logic to detect a signal level on one or more of the plurality of circuit traces comprises a look-aside register to store a signal level on one or more of the plurality of circuit traces.

5. The system of claim 3 , wherein the logic to compare the signal level to a reference signal level stored in a memory location comprises logic to retrieve an expected signal value from a data table.

6. The system of claim 1 , further comprising logic to activate an error routine when one or more signal values on one or more of the plurality of circuit traces in the second circuit assembly fails to match an expected signal value.

7. The system of claim 5 , wherein the error routine generates a signal when the cable assembly in installed incorrectly.

8. A computing system, comprising:

one or more processors;

a first circuit assembly having a plurality of circuit traces;

a second circuit assembly having a plurality of circuit traces;

a cable assembly connecting the plurality of circuit traces on the first circuit assembly to the plurality of circuit traces on the second circuit assembly;

signal generating circuitry to generate signal values on one or more of the plurality of circuit traces in the first circuit assembly; and

a memory module communicatively connected to the one or more processors and comprising logic instructions which, when executed on the one or more processors configure the one or more processors to compare signal values on one or more of the plurality of circuit traces in the second circuit assembly to an expected signal value.

9. The computing system of claim 8 , wherein the signal generating circuitry to generate signal values on one or more of the plurality of circuit traces in the first circuit assembly comprises one or more bias voltage devices connected to one or more of the plurality of circuit traces.

10. The computing system of claim 8 , wherein the further comprising:

logic to detect a signal level on one or more of the plurality of circuit traces in the second circuit assembly; and

logic instructions which, when executed, configure the processor to compare the signal level to a reference signal level stored in a memory location.

11. The computing system of claim 10 , wherein the logic to detect a signal level on one or more of the plurality of circuit traces comprises a look-aside register to store a signal level on one or more of the plurality of circuit traces.

12. The computing system of claim 10 , further comprising logic instructions which, when executed, retrieve an expected signal value from a data table.

13. The computing system of claim 8 , further comprising logic to activate an error routine when one or more signal values on one or more of the plurality of circuit traces in the second circuit assembly fails to match an expected signal value.

14. The computing system of claim 12 , wherein the error routine generates a signal when the cable assembly in installed incorrectly.

15. A method, comprising:

connecting a first circuit assembly having a plurality of circuit traces to a second circuit assembly having a plurality of circuit traces;

generating signal values on one or more of the plurality of circuit traces in the first circuit assembly;

receiving the signal values on one or more circuit traces in the second circuit assembly; and

comparing signal values on one or more of the plurality of circuit traces in the second circuit assembly to an expected signal value.

16. The method of claim 15 , wherein generating signal values on one or more of the plurality of circuit traces in the first circuit assembly comprises applying one or bias voltages to one or more of the plurality of circuit traces.

17. The method of claim 15 , wherein comparing signal values on one or more of the plurality of circuit traces in the second circuit assembly to an expected signal value comprises:

detecting a signal level on one or more of the plurality of circuit traces in the second circuit assembly; and

comparing the signal level to a reference signal level stored in a memory location.

18. The method of claim 15 , wherein detecting a signal level on one or more of the plurality of circuit traces further comprises reading a signal level on one or more of the plurality of circuit traces from a look-aside register.

19. The method of claim 15 , further comprising activating an error routine when one or more signal values on one or more of the plurality of circuit traces in the second circuit assembly fails to match an expected signal value.

20. The method of claim 19 , wherein the error routine generates a signal when the cable assembly in installed incorrectly.