Logic gate with reduced sub-threshold leak current

1. A logic gate comprising:

a first transistor for receiving a first voltage at its source, receiving a first input signal at its gate, and supplying a first output signal from its drain;

a second transistor for receiving at its source a second voltage that is lower than said first voltage, receiving a second input signal at its gate, and supplying a second output signal from its drain; and

a connection-switching unit that is connected between the drains of said first transistor and said second transistor for connecting or cutting off said first transistor and said second transistor;

said connection-switching unit including two or more transistors connected in parallel with respect to each other, each of said two or more transistors having a higher threshold voltage than a threshold voltage of said first transistor and a threshold voltage of said second transistor.

2. The logic gate according to claim 1 , wherein a control signal is applied as input to a gate of a particular transistor of said two or more transistors to turn ON said particular transistor during operation and to turn OFF said particular transistor during standby.

3. The logic gate according to claim 2 , further comprising:

a third transistor that is connected in parallel to said first transistor for receiving said control signal at its gate and receiving said first voltage at its source; and

a fourth transistor that is connected in parallel to said second transistor for receiving said control signal at its gate and receiving said second voltage at its source.

4. The logic gate according to claim 1 , wherein said first input signal and said second input signal are identical.

5. The logic gate according to claim 1 , wherein said first input signal is different from said second input signal.

6. The logic gate according to claim 1 ,

wherein said first input signal is a fall-side high-speed transition signal such that a transition at a fall-side of said first input signal occurs at a higher speed than a transition at a rise-side of said first input signal; and

wherein said second input signal is a rise-side high-speed transition signal such that a transition at a rise-side of said second input signal occurs at a higher speed than a transition at a fall-side of said second input signal.

7. The logic gate according to claim 6 ,

wherein said first output signal is a rise-side high-speed transition signal such that a transition at a rise-side of said first output signal occurs at a higher speed than a transition at a fall-side of said first output signal; and

wherein said second output signal is a fall-side high-speed transition signal such that a transition at a fall-side of said second output signal occurs at a higher speed than a transition at a rise-side of said second output signal.

8. The logic gate according to claim 1 ,

said first transistor connected to supply said first output signal to a circuit that is different from said connection-switching unit; and

said second transistor connected to supply said second output signal to said circuit.

9. The logic gate according to claim 1 ,

wherein one of said two of more transistors is connected to receive a control signal; and

wherein another one of said two or more transistors is connected to receive an inverse of said control signal.

10. A logic circuit comprising:

a logic gate comprising:

a first transistor for receiving a first voltage at its source, receiving a first input signal at its gate, and supplying a first output signal from its drain;

a second transistor for receiving at its source a second voltage that is lower than said first voltage, receiving a second input signal at its gate, and supplying a second output signal from its drain; and

a connection-switching unit that is connected between the drains of said first transistor and said second transistor for connecting or cutting off said first transistor and said second transistor; and

a detection/holding circuit that is connected to said logic gate for wave-shaping said first output signal and said second output signal that are received from said logic gate to supply one signal to an outside.

11. The logic circuit according to claim 10 , wherein said detection/holding circuit includes:

a detection unit for detecting said first output signal and said second output signal;

a holding unit for holding signals that are to be supplied to the outside during standby of said logic gate in accordance with signals supplied from said detection unit;

an output unit for, during operation of said logic gate, supplying to the outside, of said first output signal and said second output signal received from said detection unit, the signal that is received first, and during standby of said logic gate, supplying to the outside a signal that is held in said holding unit.

12. A logic circuit comprising:

a plurality of logic gates, each of said plurality of logic gates comprising:

a first transistor for receiving a first voltage at its source, receiving a first input signal at its gate, and supplying a first output signal from its drain;

a second transistor for receiving at its source a second voltage that is lower than said first voltage, a second input signal at its gate, and supplying a second output signal from its drain; and

a connection-switching unit that is connected between the drains of said first transistor and said second transistor for connecting or cutting off said first transistor and said second transistor;

said plurality of logic gates including a first logic gate and a second logic gate that is connected to said first logic gate;

wherein said first output signal of said first logic gate is applied as input to the gate of said second transistor of said second logic gate; and

wherein said second output signal of said first logic gate is applied as input to the gate of said first transistor of said second logic gate.

13. The logic circuit according to claim 12 , comprising:

a first power supply line for supplying said first voltage; and

a second power supply line that is provided parallel to said first power supply line for supplying said second voltage;

wherein said first logic gate and said second logic gate are successively arranged along said first power supply line in a region that is interposed between said first power supply line and second power supply line;

wherein, for each of said first logic gate and said second logic gate, a formation region of said first transistor and a formation region of said second transistor are arranged separated by a prescribed distance in a direction perpendicular to said first power supply line; and

wherein an order of arrangement of the formation region of said first transistor and the formation region of said second transistor is reversed for said first logic gate and said second logic gate.