Field effect transistor and method of fabricating the same
View Patent ↗Provided are a field effect transistor and a method of fabricating the same, wherein the field effect transistor is formed which has a hyperfine channel length by employing a technique for forming a sidewall spacer and adjusting the deposition thickness of a thin film. In the field effect transistor of the present invention, a source junction and a drain junction are thin, and the overlap between the source and the gate and between the drain and the gate is prevented, thereby lowering parasitic resistance. Further, the gate electric field is easily introduced to the drain extending region, so that the carrier concentration is effectively controlled in the channel at the drain. Also, the drain extending region is formed to be thinner than the source, so that the short channel characteristic is excellent.
1. A field effect transistor comprising:
a substrate;
a gate electrode on the substrate;
an asymmetrical L-shaped gate insulating layer, the gate insulating layer consisting of a first portion which extends between a lower side of the gate electrode and the substrate, and a contiguous second portion which extends up along a first side of the gate electrode;
a source layer on the substrate at one side of the gate electrode;
a drain layer on the substrate at the other side of the gate electrode;
a first insulating layer between a) the second portion of the gate insulating layer and b) the source layer;
second and third insulating layers between the gate electrode and the drain layer the second insulating layer being disposed against a second side of the gate electrode, and the third insulating layer being disposed against a side of the drain layer and a side of the second insulating layer;
a source junction on the substrate beneath the first insulating layer and the source layer;
a drain junction on the substrate beneath the drain layer; and
an extending region configured as part of the drain junction and configured to be thinner than a main portion of the drain junction and formed in the substrate beneath the third insulating layer, the first portion of the gate insulating layer separating the extending region and the third insulating layer wherein the L-shaped gate insulating layer which has a different material than the first, second, and third insulating layers.
2. The field effect transistor according to claim 1 , wherein the substrate includes any one of a bulk silicon substrate and a silicon on insulator (SOI) substrate.
3. The field effect transistor according to claim 1 , wherein the source and drain layers are formed of doped poly silicon layers.
4. The field effect transistor according to claim 1 , wherein the first and third insulating layers are formed of oxide layers, and the second insulating layer is formed of a high dielectric insulating layer.
5. The field effect transistor according to claim 4 , wherein the high dielectric insulating layer is formed of one selected from a group consisting of Al 2 O 3 , ZrSi x O y , HfSi x O y , HfAl x O y , LaSi x O y , ZrAl x O y , ZrN x O y , ZrO 2 , HfO 2 , La 2 O 3 , Pr 2 O 3 , Ta 2 O 5 , and a compound thereof.
6. The field effect transistor according to claim 1 , wherein the second insulating layer is thicker than the second portion of the gate insulating layer.
7. The field effect transistor according to claim 1 , wherein the source junction extends deeper into the substrate than the drain junction so as to be thicker than the drain junction.
8. The field effect transistor according to claim 1 , wherein the second and third insulating layers are located side by side and on top of the gate insulating layer.
9. A field effect transistor comprises:
a substrate;
a gate electrode on the substrate;
an asymmetrical L-shaped gate insulating layer, the gate insulating layer consisting of a first portion which extends between a lower side of the gate electrode and the substrate, and a contiguous second portion which extends up along a first side of the gate electrode;
a source layer on the substrate at one side of the gate electrode;
a drain layer on the substrate at the other side of the gate electrode;
a first insulating layer between a) the second portion of the gate insulating layer and b) the source layer;
second and third insulating layers between the gate electrode and the drain layer the second insulating layer being disposed against a second side of the gate electrode, and the third insulating layer being disposed against a side of the drain layer and a side of the second insulating layer, the second insulating layer being different from the third insulating layer and comprising at least of one of Al 2 O 3 , ZrSi x O y , HfSi x O y , HfAl x O y , LaSi x O y , ZrAl x O y , ZrN x O y , ZrO 2 , HfO 2 , La 2 O 3 , Pr 2 O 3 , Ta 2 O 5 , and a compound thereof;
a source junction on the substrate beneath the first insulating layer and the source layer;
a drain junction on the substrate beneath the drain layer; and
an extending region configured as part of the drain junction and configured to be thinner than a main portion of the drain junction and formed in the substrate beneath the third insulating layer, the first portion of the gate insulating layer separating the extending region and the third insulating layer wherein the L-shaped gate insulating layer which has a different material than the first, second, and third insulating layers.