Decimating down converter and related methods
View Patent ↗A system of downconverting an intermediate frequency (IF) phase or frequency modulated signal to a digital baseband includes an N bit shift register circuit that receives a binary input as a 1-bit input sample data stream of an IF signal. A decimation circuit includes a memory and receives data from the N bit shift register circuit and stores N 1-bit binary samples as address bits and performs decimation, downconversion and filtering by accessing memory values at a predetermined rate.
1. A system of downconverting an intermediate frequency (IF) phase, frequency or amplitude modulated signal or combination to a digital baseband, comprising:
an N bit shift register circuit that receives a binary input as a 1-bit input sample data stream of an IF signal; and
a decimation circuit that includes a memory and receives data from the N bit shift register circuit and stores N 1-bit binary samples as address bits and performs decimation by accessing memory values at a predetermined rate and performs a multiplication process of the 1-bit input sample data stream and a complex local oscillator (LO) data stream.
2. A system according to claim 1 , wherein said decimation circuit is operative as a look-up table to perform the multiplication process.
3. A system according to claim 2 , wherein address bits in the decimation circuit are indicative of a complex local oscillator (LO) phase.
4. A system according to claim 1 , and further comprising a summer circuit operatively connected to said decimation circuit to create a single output for a time sample.
5. A system according to claim 4 , and further comprising a low pass filter that receives data from said summer circuit.
6. A system according to claim 5 , wherein said low pass filter circuit comprises a matched filter.
7. A system according to claim 1 , wherein said memory of said decimation circuit comprises a block random access memory (RAM).
8. A system of downconverting an intermediate frequency (IF) phase, frequency or amplitude modulated signal or combination to a digital baseband, comprising:
a plurality of N bit shift registers arranged to receive a binary input as a 1-bit input sample data stream of an IF signal and shift data a predetermined number of times; and
a decimation circuit formed from individual memory circuits that connect respective ones of the shift registers and receive data from the N bit shift registers and store N 1-bit binary samples as address bits and perform decimation by accessing memory values at a predetermined rate and performs a multiplication process of the 1-bit input sample data stream and a complex local oscillator (LO) data stream.
9. A system according to claim 8 , wherein said decimation circuit is operative as a look-up table to perform the multiplication process.
10. A system according to claim 9 , wherein address bits in the decimation circuit are indicative of a complex local oscillator (LO) phase.
11. A system according to claim 8 , and further comprising a summer circuit operatively connected to said decimation circuit to create a single output for a time sample.
12. A system according to claim 11 , and further comprising a low pass filter that receives data from said summer circuit.
13. A system according to claim 12 , wherein said low pass filter circuit comprises a matched filter.
14. A system according to claim 8 , wherein said memory of said decimation circuit comprises a block random access memory (RAM).
15. A method of downconverting an intermediate frequency (IF) phase, frequency or amplitude modulated signal or combination to a digital baseband, which comprises:
sampling the IF signal using a 1-bit representation to form a 1-bit input sample data stream;
storing N 1-bit binary samples as address bits to a memory; and
performing decimation on the 1-bit input sample data stream by accessing memory values at a predetermined rate and performing a multiplication process of the 1-bit input sample data stream and a complex local oscillator (LO) data stream.
16. A method according to claim 15 , which further comprises using memory as a look up table to perform the multiplication process.
17. A method according to claim 15 , which further comprises loading the memory with a precomputed sum of possible binary input values multiplied by a current phase of a complex local oscillator.
18. A method according to claim 15 , which further comprises multiplying the values of block RAM by a filter impulse response such that the output is the output sample at that time.
19. A method according to claim 15 , which further comprises limiting the IF signal to a frequency or phase modulated square wave signal before sampling the signal.
20. A method according to claim 15 , which further comprises controlling the phase of a complex local oscillator with 4 phase bits.
21. A method according to claim 15 , which further comprises running a shift register at an input sampling rate.
22. A method according to claim 15 , which further comprises clocking the decimation circuit at a lower decimation rate.
23. A method according to claim 15 , which further comprises indicating a complex local oscillator phase by address bits for the decimation circuit.
24. A method according to claim 15 , which further comprises receiving data within a plurality of N bit shift registers operative with the decimation circuit.