Semiconductor integrated circuit device manufacturing method
View Patent ↗To reduce variation in channel lengths of MOS transistors within a circuit functional module. When exposure of a wafer substrate having a semiconductor integrated circuit device 1 including a plurality of CMOS circuit module regions CCM 11 to CCM 22 to be subject to substrate bias control formed in a core region 10 is performed using a step-and-scan type projection exposure apparatus, scanning is performed in the same direction as a longitudinal direction of the respective CMOS circuit module regions CCM 11 to CCM 22 . In this device, a gate insulating film is formed on the substrate, a gate electrode material film is formed on the gate insulating film, and a photoresist film is formed on the gate electrode material film.
1. A semiconductor integrated circuit device manufacturing method comprising the steps of:
(a) providing a wafer substrate including a semiconductor integrated circuit device having a plurality of CMOS circuit module regions formed in a core region thereof, said CMOS circuit module regions being subject to substrate bias control, said semiconductor integrated circuit device being configured to include a gate insulating film formed on said substrate, a gate electrode material film formed on said gate insulating film, and a photoresist film formed on said gate electrode material film; and
(b) exposing said wafer substrate using a step-and-scan type projection exposure apparatus;
wherein upon said exposing, scanning is performed in a same direction as a longitudinal direction of each of said CMOS circuit module regions in said core region.
2. The semiconductor integrated circuit device according to claim 1 , wherein a gate pattern associated with circuit functional modules of said CMOS circuit module regions in said core region is formed in a photomask used at a time of the exposure by said step-and-scan type projection exposure apparatus, and a longitudinal direction of said gate pattern is arranged in a same direction as a scan direction of said step-and-scan type projection exposure apparatus.
3. A semiconductor integrated circuit device manufacturing method comprising the steps of:
(a) providing a wafer substrate including a semiconductor integrated circuit device having a plurality of CMOS circuit module regions formed in an input/output region thereof, said CMOS circuit module regions being subject to substrate bias control, said semiconductor integrated circuit device being configured to include a gate insulating film formed on said substrate, a gate electrode material film formed on said gate insulating film, and a photoresist film formed on said gate electrode material film; and
(b) exposing said wafer substrate using a step-and-scan type projection exposure apparatus,
wherein upon said exposing, scanning is performed in a same direction as a direction of boundaries between said CMOS circuit module regions being adjacent to one another in said input/output region.
4. The semiconductor integrated circuit device manufacturing method according to claim 3 , wherein a gate pattern associated with circuit functional modules of said CMOS circuit module regions in said input/output region is formed in a photomask used at a time of the exposure by said step-and-scan type projection exposure apparatus, and a longitudinal direction of said gate pattern is arranged in a same direction as a scan direction of said step-and-scan type projection exposure apparatus.