ESD protection circuit with SCR structure for semiconductor device

1. An ESD protection structure, comprising:

a first P-type semiconductor region connected to a pad;

a first N-type semiconductor region coupled with said first P-type semiconductor region;

a second P-type semiconductor region coupled with said first N-type semiconductor region and connected to a ground terminal;

a second N-type semiconductor region coupled with said second P-type semiconductor region and connected to a ground terminal;

a trigger circuit configured to draw a trigger current from said first N-type semiconductor region when a surge is applied to said pad;

a resistive element electrically connected between the trigger circuit and the first N-type semiconductor region; and

a shallow trench isolation region configured to electrically insulate the tripper circuit and the first N-type semiconductor region,

wherein the resistive element is provided over the shallow trench isolation region.

2. The ESD protection structure according to claim 1 , wherein said first P-type semiconductor region, said first N-type semiconductor region, said second P-type semiconductor region and said second N-type semiconductor region are integrated on a semiconductor substrate, and said resistive element is formed outside of said semiconductor substrate.

3. The ESD protection structure according to claim 2 , wherein said resistive element comprises a structure including a polysilicon layer.

4. The ESD protection structure according to claim 1 , wherein said resistive element comprises of a layer or a multilayer whose sheet resistance is equal to or higher than 1.0 Ω/sq.

5. The ESD protection structure according to claim 1 ,

wherein said first N-type semiconductor region comprises an N-well formed in a semiconductor substrate,

wherein said first P-type semiconductor region comprises a P+ diffusion layer formed in said N-well,

wherein said second P-type semiconductor region comprises a P-type region which is a part of said semiconductor substrate, and

wherein said second N-type semiconductor region comprises an N+ diffusion layer formed in said semiconductor substrate.

6. The ESD protection structure according to claim 1 , wherein said trigger circuit comprises an NMOS transistor whose drain is connected to said first N-type semiconductor region through said resistive element.

7. The ESD protection structure according to claim 6 , wherein a gate and a source of said NMOS transistor are connected to a ground terminal.

8. The ESD protection structure according to claim 6 ,

wherein a source of said NMOS transistor is connected to a ground terminal, and

wherein a gate of said NMOS transistor is connected to a power supply terminal through at least one MOS transistor and to a ground terminal through at least one MOS transistor.

9. The ESD protection structure according to claim 6 , wherein a gate of said NMOS transistor is electrically connected to said first N-type semiconductor region through said resistive element via a first wire element that connects the gate of said NMOS transistor to the resistive element end via a second wire element that connects the resistive element to the first N-type semiconductor region.

10. The ESD protection structure according to claim 1 , wherein said trigger circuit comprises a PMOS transistor whose source is connected to said first N-type semiconductor region through said resistive element.

11. The ESD protection structure according to claim 10 , wherein a gate of said PMOS transistor is electrically connected to said first N-type semiconductor region through said resistive element via a first wire element that connects the gate of said NMOS transistor to the resistive element and via a second wire element that connects the resistive element to the first N-type semiconductor region.

12. The ESD protection structure according to claim 10 ,

wherein a gate of said PMOS transistor is connected to a drain thereof, and

wherein said drain of said PMOS transistor is connected to a ground terminal directly or through another PMOS transistor.

13. The ESD protection structure according to claim 1 , wherein said trigger circuit comprises a plurality of diodes which are connected in series in a forward direction from said resistive element to a ground terminal.

14. The ESD protection structure according to claim 1 , further comprising a shallow trench isolation layer provided between the the first N-type semiconductor region to the second N-type semiconductor region,

wherein the resistive element is provided on the shallow trench isolation layer.

15. The ESD protection structure according to claim 14 , wherein the resistive element electronically connects the first N-type semiconductor region to the second N-type semiconductor region.

16. The ESD protection structure according to claim 14 , wherein the resistive element comprises a polysilicon layer provided on the shallow trench isolation layer and a silicide layer provided on the polysilicon layer.

17. The ESD protection structure according to claim 14 , wherein the polysilicon layer is provided on a shallow trench isolation layer.

18. The ESD protection structure according to claim 1 , wherein the resistive element electronically connects the first N-type semiconductor region to the second N-type semiconductor region, and

wherein the resistive element comprises a polysilicon layer and a silicide layer provided on the polysilicon layer.

19. The ESD protection structure according to claim 8 , wherein the trigger circuit further comprises an inverter comprising a PMOS transistor electrically connected in series between the power supply terminal and the ground terminal, and another NMOS transistor.

20. The ESD protection structure according to claim 19 , wherein when a semiconductor device electrically connected to the ESD is not powered on, the power supply terminal is in a floating state and both the PMOS transistor and the another NMOS transistor of the inverter are not completely turned off.