IP Library Granted Patent US 7,592,790
Granted Patent B2
US 7,592,790 · App. 11/406,309 · Granted Sep 22, 2009

Start-up circuit with feedforward compensation for power converters

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Quick Facts
Patent No.
US 7,592,790
App. No.
11/406,309
Granted
Sep 22, 2009
Kind
B2
Abstract

A bleeding resistor is required to discharge EMI filter of the power converter for the safety purpose. In order to save power and reduce device count, the present invention further uses this bleeding resistor for both start-up and feedforward compensation. It includes an input terminal for connecting the bleeding resistor. A voltage divider is connected to the input terminal. A sample-and-hold circuit samples and holds a voltage signal from the voltage divider. After that, a low-pass filter is connected to the sample-and-hold circuit to generate an offset signal in accordance with the voltage signal. The offset signal is connected to a limit circuit to generate a limit signal that limits the switching current of the power converter.

Claims (45)

1. A start-up circuit, comprising:

an input terminal coupled to an input voltage of a power converter via a bleeding resistor;

a diode coupled from the input terminal to a supply terminal of a control circuit of the power converter for providing power source to the control circuit;

a voltage divider coupled to the input terminal via a switch;

a sample-and-hold circuit coupled to the voltage divider to sample and hold a voltage signal from the voltage divider;

a low-pass filter coupled to the sample-and-hold circuit to generate an offset signal in accordance with the voltage signal; and

an adder coupled to the low-pass filter to generate a limit signal in accordance with a reference signal and the offset signal;

wherein the limit signal is utilized to limit a switching current of the power converter.

2. The start-up circuit as claimed in claim 1 , in which the voltage divider includes resistors connected in series.

3. The start-up circuit as claimed in claim 1 , in which the sample-and-hold circuit comprising:

a first sample switch connected to the voltage divider; and

a first capacitor connected to the first sample switch to generate the voltage signal;

wherein the first sample switch is controlled by a first sample signal that is divided from a switching signal of the power converter.

4. The start-up circuit as claimed in claim 3 , in which the low pass filter comprising:

a second sample switch connected to the first capacitor of the sample-and-hold circuit; and

a second capacitor connected to the second sample switch to generate the offset signal;

wherein the second sample switch is controlled by a second sample signal that is synchronized with the first sample signal.

5. The start-up circuit as claimed in claim 4 , in which the capacitance of the second capacitor is higher than the capacitance of the first capacitor.

6. A circuit with line voltage detection, comprising:

an input terminal coupled to an input voltage of a power converter via a bleeding resistor;

a voltage divider coupled to the input terminal;

a sample-and-hold circuit coupled to the voltage divider to sample and hold a voltage signal from the voltage divider;

a low-pass filter coupled to the sample-and-hold circuit to generate an offset signal in accordance with the voltage signal; and

a limit circuit coupled to the low-pass filter to generate a limit signal in response to the offset signal;

wherein the limit signal limits a switching current of the power converter.

7. The circuit with line voltage detection as claimed in claim 6 , in which the voltage divider includes resistors.

8. The circuit with line voltage detection as claimed in claim 6 , in which the sample-and-hold circuit comprising:

a first sample switch connected to the voltage divider; and

a first capacitor connected to the first sample switch to generate the voltage signal;

wherein the first sample switch is controlled by a first sample signal that is divided from a switching signal of the power converter.

9. The circuit with line voltage detection as claimed in claim 8 , in which the low pass filter comprising:

a second sample switch connected to the first capacitor of the sample-and-hold circuit; and

a second capacitor connected to the second sample switch to generate the offset signal;

wherein the second sample switch is controlled by a second sample signal that is synchronized with the first sample signal.

10. The circuit with line voltage detection as claimed in claim 9 , in which the capacitance of the second capacitor is higher than the capacitance of the first capacitor.

11. A circuit with detection, comprising:

an input terminal coupled to an input voltage of a power converter;

a voltage divider coupled to the input terminal;

a sample-and-hold circuit coupled to the voltage divider to sample and hold a voltage signal from the voltage divider; and

a limit circuit generating a limit signal in response to the voltage signal;

wherein the limit signal limits a switching current of the power converter.

12. The circuit with detection as claimed in claim 11 , in which the sample-and-hold circuit comprising:

a first sample switch connected to the voltage divider; and

a first capacitor connected to the first sample switch to generate the voltage signal;

wherein the first sample switch is controlled by a first sample signal that is divided from a switching signal of the power converter.

Assignments (5)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT RECORDED AT REEL 046410, FRAME 0933 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064072/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 22, 2018
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 046410/0933 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 25, 2017
From: FAIRCHILD (TAIWAN) CORPORATION (FORMERLY SYSTEM GENERAL CORPORATION)
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 042328/0318 →
CHANGE OF NAME Recorded Jun 8, 2016
From: SYSTEM GENERAL CORP.
To: FAIRCHILD (TAIWAN) CORPORATION
Reel/Frame 038906/0030 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 24, 2006
From: YANG, TA-YUNG
To: SYSTEM GENERAL CORP.
Reel/Frame 017528/0263 →