Transitioning the state of phase change material by annealing
A semiconductor device includes a preprocessed wafer and an annealed phase change material layer contacting the preprocessed wafer. The semiconductor device includes a first material layer contacting the annealed phase change material layer.
1 . A semiconductor device comprising:
a preprocessed wafer;
an annealed phase change material layer contacting the preprocessed wafer; and
a first material layer contacting the annealed phase change material layer.
2 . The semiconductor device of claim 1 , wherein the semiconductor device comprises a phase change memory.
3 . The semiconductor device of claim 1 , wherein the annealed phase change material layer is defined by having been transitioned from an amorphous state to a crystalline state.
4 . The semiconductor device of claim 3 , wherein the crystalline state comprises a face-centered cubic crystalline state.
5 . The semiconductor device of claim 3 , wherein the crystalline state comprises a hexagonal closest packing crystalline state.
6 . The semiconductor device of claim 1 , wherein the first material layer comprises a conductive material.
7 . The semiconductor device of claim 1 , wherein the first material layer comprises an insulator material.
8 . A phase change memory comprising:
a preprocessed wafer;
an annealed phase change material layer contacting the preprocessed wafer; and
an electrode material layer contacting the annealed phase change material layer.
9 . The semiconductor device of claim 8 , wherein the phase change material layer comprises at least one of Ge, Sb, Te, Ga, As, In, Se, and S.
10 . The semiconductor device of claim 8 , wherein the phase change material layer comprises Ge 2 Sb 2 Te 5 .
11 . The semiconductor device of claim 8 , wherein the electrode material layer comprises one of Ti, TiN, Ta, TaN, W, Al, and Cu.
12 . A semiconductor device comprising:
a preprocessed wafer;
a phase change material layer deposited on the preprocessed wafer;
a first material layer deposited on the phase change material layer; and
means for preventing the first material layer from peeling.
13 . The semiconductor device of claim 12 , wherein the semiconductor device comprises a phase change memory.
14 . The semiconductor device of claim 12 , wherein the phase change material layer comprises at least one of Ge, Sb, Te, Ga, As, In, Se, and S.
15 . The semiconductor device of claim 12 , wherein the phase change material layer comprises Ge 2 Sb 2 Te 5 .
16 . The semiconductor device of claim 12 , wherein the first material layer comprises one of Ti, TiN, Ta, TaN, W, Al, and Cu.
17 . A method for fabricating a semiconductor device, the method comprising:
providing a preprocessed wafer;
depositing a phase change material layer in an amorphous state over the preprocessed wafer; and
annealing the phase change material layer to transition the phase change material from the amorphous state to a crystalline state.
18 . The method of claim 17 , wherein annealing the phase change material layer comprises in-situ annealing of the phase change material layer.
19 . The method of claim 17 , wherein annealing the phase change material layer comprises ex-situ annealing of the phase change material layer.
20 . The method of claim 17 , wherein annealing the phase change material layer comprises thermally annealing the phase change material layer.
21 . The method of claim 17 , wherein annealing the phase change material layer comprises heating the phase change material layer.
22 . The method of claim 17 , further comprising:
depositing a first material layer over the phase change material layer.
23 . A method for fabricating a phase change memory, the method comprising:
providing a preprocessed wafer including transistors and contact plugs;
depositing a phase change material layer in an amorphous state over the preprocessed wafer; and
annealing the phase change material layer to transition the phase change material from the amorphous state to a crystalline state.
24 . The method of claim 23 , wherein depositing the phase change material layer comprises depositing a material including at least one of Ge, Sb, Te, Ga, As, In, Se, and S.
25 . The method of claim 23 , wherein depositing the phase change material layer comprises depositing Ge 2 Sb 2 Te 5 .
26 . The method of claim 23 , further comprising:
depositing an electrode material layer over the phase change material layer.
27 . The method of claim 26 , wherein depositing the electrode material layer comprises depositing one of Ti, TiN, Ta, TaN, W, Al, and Cu.
28 . A method of fabricating a resistive memory device, comprising:
depositing a phase change material in a first state and having a first volume on a preprocessed wafer;
transitioning the phase change material from the first state to a second state in which the phase change material has a second volume which is less than the first volume;
depositing a first material on the phase change material in the second state.
29 . The method of claim 28 , wherein the transitioning includes annealing the phase change material.
30 . The method of claim 29 , wherein the annealing comprises an in-situ annealing.
30 . The method of claim 28 , wherein the transitioning includes transitioning from an amorphous first state to a face-centered cubic (FCC) crystalline second state.
31 . The method of claim 28 , wherein the transitioning includes transitioning from an amorphous first state to a hexagonal closest packing (HCP) crystalline second state.
32 . The method of claim 28 , wherein the first material forms an electrode.
33 . An apparatus for, fabricating a semiconductor device, the apparatus comprising:
means for depositing a phase change material in a first state and having a first volume on a preprocessed wafer;
means for transitioning the deposited phase change material from the first state to a second state in which the phase change material has a second volume which is less than the first volume;
means for depositing a first material on the deposited phase change material in the second state.
34 . A resistive memory device comprising:
a preprocessed wafer;
a phase change material deposited on the preprocessed wafer in a first state and transitioned to a second state after deposition, the phase change material having a lesser volume in the second state than in the first state; and
a first material deposited on the phase change material when the phase change material is in the second state.
35 . The resistive memory device of claim 34 , wherein the first state comprises an amorphous state and the second state comprises a face-centered cubic (FCC) crystalline second achieved through an annealing process.
36 . The resistive memory device of claim 34 , wherein the first state comprises an amorphous state and the second state comprises a hexagonal closest packing (HCP) crystalline state achieved through an annealing process.