Semiconductor memory device using row redundancy and I/O redundancy scheme based on a preset order and a defect order
View Patent ↗To reduce the area relating to location of redundant elements for relieving defects of a memory. A memory device has row address and input/output data as two dimensional redundancy parameters for relieving defects of an embedded memory 30 . It comprises a built-in self-test circuit 10 for testing defects of the embedded memory 30 , a redundant element location operator 20 for determining which redundant element replaces a defect based on a preset order and according to the order in which defects are detected by the self-test circuit 10 , and a row redundancy unit 31 and an I/O redundancy unit 32 for replacing the defects in the embedded memory according to the determined order. The redundant element location operator 20 determines the priority axis according to the preset order and according to the order in which the defects are detected, and holds redundant element location information.
1. A semiconductor memory device having a row redundancy unit and an I/O redundancy unit as two dimensional redundancy units for relieving defects of an embedded memory,
said row redundancy unit including redundant memory cell groups that replace memory cell rows addressed by row addresses, and
said I/O redundancy unit including redundant memory cell groups that replace memory cell groups provided for every input/output data,
wherein said memory device comprises:
a built-in self-test circuit that tests an embedded memory,
a redundant element location operator that selects a redundant memory cell group from said row redundancy unit and said I/O redundancy unit based on a preset order and according to the order in which defects are detected by said self-test circuit, and
a redundancy replacement unit that replaces defects in said embedded memory with said redundant memory cell group selected by said redundant element location operator.
2. The semiconductor memory device as defined in claim 1 wherein said redundant element location operator comprises a latch circuit that stores the address of said defect replaced in said embedded memory and an address overlap determining circuit that detects a coincidence between a defect address detected by said self-test circuit and the address of said defect stored in said latch circuit, and said latch circuit latches said defect address detected when no coincidence is detected.
3. The semiconductor memory device as defined in claim 2 wherein said redundant element location operator further comprises a shift register circuit that shifts a predetermined signal and outputs a pulse signal for said latch circuit to latch said defect address every time said coincidence detection indicates that there is no overlap.
4. The semiconductor memory device as defined in claim 2 wherein said redundant element location operator comprises a counter circuit that counts the number of times that said coincidence detection indicates that there is no overlap, and a decoder circuit that receives and decodes outputs as many as the number of bits of said counter circuit and outputs a pulse signal for said latch circuit to latch said defect address.