Display driver circuit and display apparatus
A driver circuit includes an analog voltage signal generating circuit configured to generate first and second groups of analog voltage signals; a first D/A converter configured to operate in a first voltage range between a first voltage and a second voltage which is lower than the first voltage, and to output a first one of the first group of analog voltage signals based on a lower bit group of an input digital signal; and a second D/A converter configured to operate in a second voltage range between the second voltage and a third voltage which is lower than the second voltage, and to output a second one of the second group of analog voltage signals based on the lower bit group out. A selecting circuit selects one of the first analog voltage signal and the second analog voltage signal as an analog voltage selection signal based on an upper bit group of the digital signal.
1 . A driver circuit comprising:
an analog voltage signal generating circuit configured to generate first and second groups of analog voltage signals;
a first D/A converter configured to operate in a first voltage range between a first voltage and a second voltage which is lower than said first voltage, and to output a first one of said first group of analog voltage signals based on a lower bit group of an input digital signal;
a second D/A converter configured to operate in a second voltage range between said second voltage and a third voltage which is lower than said second voltage, and to output a second one of said second group of analog voltage signals based on said lower bit group out; and
a selecting circuit configured to select one of said first analog voltage signal and said second analog voltage signal as an analog voltage selection signal based on an upper bit group of said digital signal.
2 . The driver circuit according to claim 1 , wherein said second voltage is a system ground voltage.
3 . The driver circuit according to claim 1 , wherein said selecting circuit operates in a third voltage range between a voltage higher than said first voltage and a voltage lower than said third voltage.
4 . The driver circuit according to claim 1 , further comprising:
a buffer provided between said selecting circuit and an output terminal and configured to operate in a third voltage range between said first voltage and said fourth voltage.
5 . The driver circuit according to claim 1 , further comprising:
a precharging circuit configured to precharge a wiring line between said selecting circuit and an output terminal to a predetermined voltage.
6 . The driver circuit according to claim 5 , wherein said wiring line is precharged when a value of said upper bit group is changed.
7 . The driver circuit according to claim 6 , wherein when the value of said upper bit group is changed, said precharge is carried out after said selecting circuit disconnects said precharging circuit from said first and second D/A converters.
8 . The driver circuit according to claim 5 , wherein said predetermined voltage is said second voltage.
9 . The driver circuit according to claim 1 , wherein each of said first D/A converter, said second D/A converter, and said selecting circuit has a MOS transistor, and
gate insulating films of said MOS transistors in said first and second D/A converters are thinner than a gate insulating film of said MOS transistor in said selecting circuit.
10 . The driver circuit according to claim 1 , wherein each of said first D/A converter, said second D/A converter, and said selecting circuit has a MOS transistor, and
gate lengths of said MOS transistors in said first and second D/A converters are shorter than a gate length of said MOS transistor in said selecting circuit.
11 . A driver circuit comprising:
an analog voltage signal generating circuit configured to generate first to fourth groups of analog voltage signals;
a first D/A converter configured to operate in a first voltage range between a first voltage and a second voltage which is lower than said first voltage, and to output a first one of said first group of analog voltage signals based on a lower bit group of an input digital signal;
a second D/A converter configured to operate in a second voltage range between said second voltage and a third voltage which is lower than said second voltage, and to output a second one of said second group of analog voltage signals based on said lower bit group out;
a third D/A converter configured to operate in a third voltage range between a third voltage and a fourth voltage which is lower than said third voltage, and to output a third one of said first group of analog voltage signals based on a lower bit group of an input digital signal;
a fourth D/A converter configured to operate in a fourth voltage range between said fourth voltage and a fifth voltage which is lower than said fourth voltage, and to output a fourth one of said fourth group of analog voltage signals based on said lower bit group out;
a first selecting circuit configured to select one of said first analog voltage signal and said second analog voltage signal as a first analog voltage selection signal based on an upper bit group of said digital signal; and
a second selecting circuit configured to select one of said third analog voltage signal and said fourth analog voltage signal as a second analog voltage selection signal based on said upper bit group of said digital signal.
12 . The driver circuit according to claim 11 , wherein said third voltage is a system ground voltage.
13 . The driver circuit according to claim 11 , wherein said first selecting circuit operates in a fifth voltage range between a sixth voltage higher than said first voltage and said third voltage, and
said second selecting circuit operates in a sixth voltage range between said third voltage and a seventh voltage lower than said fifth voltage.
14 . The driver circuit according to claim 11 , further comprising:
a third selecting circuit configured to select one of said first analog voltage selection signal and said second analog voltage selection signal as an analog voltage selection signal based on said upper bit group of said digital signal; and
a buffer provided between said third selecting circuit and an output terminal and configured to operate in a seven voltage range between said sixth voltage and said seventh voltage.
15 . The driver circuit according to claim 11 , further comprising:
an output switching circuit configured to output one of said first analog voltage selection signal and said second analog voltage selection signal as an analog voltage selection signal to one of adjacent output terminals and the other of the selection signals to the other of the adjacent output terminals based on a polarity signal.
16 . The driver circuit according to claim 15 , further comprising:
a precharging circuit provided between said first and second selecting circuits and said output switching circuit and configured to precharge first wiring lines between said first and second selecting circuits and said output switching circuit to first and second predetermined voltages, and second wiring lines between said first wiring lines and said output terminals to a third predetermined voltage.
17 . The driver circuit according to claim 16 , wherein said first wiring lines are precharged when a value of said upper bit group is changed, and said second wiring lines are precharged in response to a polarity signal.
18 . The driver circuit according to claim 17 , wherein when the value of said upper bit group is changed, said precharge is carried out after said first and second selecting circuits disconnect said precharging circuit from said first to fourth D/A converters.
19 . The driver circuit according to claim 16 , wherein said first predetermined voltage is said second voltage, said second predetermined voltage is said fourth voltage, and said third predetermined voltage is a ground voltage.
20 . The driver circuit according to claim 16 , wherein each of said first to fourth D/A converter, said first and second selecting circuit, said precharging circuit, and said output switching circuit has a MOS transistor,
gate insulating films of said MOS transistors in said first to fourth D/A converters are thinner than gate insulating films of said MOS transistors in said first and second selecting circuits, and
the gate insulating films of said MOS transistors in said first and second selecting circuits are thinner than a gate insulating film of said MOS transistor in said output switching circuit.
21 . The driver circuit according to claim 16 , wherein each of said first to fourth D/A converter, said first and second selecting circuit, said precharging circuit, and said output switching circuit has a MOS transistor,
gate lengths of said MOS transistors in said first to fourth D/A converters are shorter than gate lengths of said MOS transistors in said first and second selecting circuits, and
the gate lengths of said MOS transistors in said first to fourth D/A converters are shorter than a gate length of said MOS transistor in said output switching circuit.
22 . A display apparatus comprising:
a display panel having data lines; and
a driver circuit configured to drive said display panel based on a digital signal by driving said data lines,
wherein said driver circuit comprises:
a logic circuit configured to latch said digital signal having a lower bit group and a higher bit group;
an analog voltage signal generating circuit configured to generate first and second groups of analog voltage signals; and
a digital-to-analog (D/A) converting circuit configured to drive said data lines based on said digital signal by using said first and second groups of analog voltage signals,
said D/A converting circuit comprises:
a first D/A converter configured to operate in a first voltage range between a first voltage and a second voltage which is lower than said first voltage, and to output a first one of said first group of analog voltage signals based on said lower bit group of an input digital signal;
a second D/A converter configured to operate in a second voltage range between said second voltage and a third voltage which is lower than said second voltage, and to output a second one of said second group of analog voltage signals based on said lower bit group out; and
a first selecting circuit configured to operate in a third voltage range between a voltage higher than said first voltage and a voltage lower than said third voltage, and to select one of said first analog voltage signal and said second analog voltage signal as a first analog voltage selection signal based on said upper bit group of said digital signal.
23 . The display apparatus according to claim 22 , wherein said /A converting circuit further comprises:
a buffer configured to drive one of said data lines based on said first analog voltage selection signal.
24 . The display apparatus according to claim 22 , wherein said analog voltage signal generating circuit further generates third and fourth groups of analog voltage signals in addition to said first and second groups of analog voltage signals, and
said D/A converting circuit further comprises:
a third D/A converter configured to operate in a third voltage range between a third voltage and a fourth voltage which is lower than said third voltage, and to output a third one of said first group of analog voltage signals based on a lower bit group of an input digital signal;
a fourth D/A converter configured to operate in a fourth voltage range between said fourth voltage and a fifth voltage which is lower than said fourth voltage, and to output a fourth one of said fourth group of analog voltage signals based on said lower bit group out;
a second selecting circuit configured to select one of said third analog voltage signal and said fourth analog voltage signal as a second analog voltage selection signal based on said upper bit group of said digital signal; and
an output switching circuit configured to output one of said first analog voltage selection signal and said second analog voltage selection signal as an analog voltage selection signal to one of adjacent output terminals and the other of the selection signals to the other of the adjacent output terminals based on a polarity signal.
25 . The display apparatus according to claim 22 , further comprising:
a level shift circuit group provided between said logic circuit and said D/A converting circuit, and comprising first to third level shift circuits,
wherein said first level shift circuit receives said lower bit group from said logic circuit, and outputs said lower bit group to said first D/A converter after converting said lower bit group to fit with said first voltage range,
said second level shift circuit receives said lower bit group from said logic circuit, and outputs said lower bit group to said second D/A converter after changing said lower bit group to fit with said second voltage range, and
said third level shift circuit receives said upper bit group from said logic circuit, and outputs said upper bit group to said first selecting circuit after changing said upper bit group to fit with said third voltage range.
26 . The display apparatus according to claim 24 , further comprising:
a level shift circuit group provided between said logic circuit and said D/A converting circuit, and comprising first to seventh level shift circuits,
wherein said first level shift circuit receives said lower bit group from said logic circuit, and outputs said lower bit group to said first D/A converter after converting said lower bit group to fit with said first voltage range,
said second level shift circuit receives said lower bit group from said logic circuit, and outputs said lower bit group to said second D/A converter after changing said lower bit group to fit with said second voltage range,
said third level shift circuit receives said lower bit group from said logic circuit, and outputs said lower bit group to said third D/A converter after converting said lower bit group to fit with said third voltage range,
said fourth level shift circuit receives said lower bit group from said logic circuit, and outputs said lower bit group to said fourth D/A converter after changing said lower bit group to fit with said fourth voltage range,
said fifth level shift circuit receives said upper bit group from said logic circuit, and outputs said upper bit group to said first selecting circuit after changing said upper bit group to fit with said fifth voltage range,
said sixth level shift circuit receives said upper bit group from said logic circuit, and outputs said upper bit group to said second selecting circuit after changing said upper bit group to fit with said sixth voltage range, and
said seventh level shift circuit receives a polarity signal from said logic circuit, and outputs said polarity signal to said output switching circuit after changing said polarity signal to fit with said seventh voltage range.