Integrated camera image signal processor and video encoder
An apparatus including a first circuit and a second circuit. The first circuit may be configured to perform image signal processing using encoding related information. The second circuit may be configured to encode image data using image signal processing related information, wherein said first circuit is further configured to pass said image signal processing related information to said second circuit and said second circuit is further configured to pass said encoding related information to said first circuit.
1. An apparatus comprising:
a first circuit configured to receive an input signal and perform image signal processing on said input signal using encoding related information;
a second circuit configured to encode image data using image signal processing related information, wherein said first circuit is further configured to pass (i) said image data and (ii) said image signal processing related information to said second circuit and said second circuit is further configured to pass said encoding related information to said first circuit and present a picture data output signal; and
wherein said encoding related information comprises commands configured to modify one or more processing parameters of said first circuit.
2. The apparatus according to claim 1 , wherein said first and said second circuits are integrated in a single integrated circuit.
3. The apparatus according to claim 1 , wherein said second circuit comprises one or more circuits selected from the group consisting of a video picture encoder circuit, a still picture encoder circuit, a video picture encoder/decoder (CODEC) circuit and a still picture encoder/decoder (CODEC).
4. The apparatus according to claim 3 , wherein said video picture CODEC comprises an H.264 complaint CODEC.
5. The apparatus according to claim 3 , wherein said still picture CODEC comprises a JPEG compliant CODEC.
6. The apparatus according to claim 1 , wherein said first circuit comprises an image signal processing (ISP) circuit.
7. The apparatus according to claim 1 , wherein said first circuit comprises a digital signal processor (DSP).
8. The apparatus according to claim 1 , wherein said first circuit and said second circuit are further configured to (i) receive one or more first control signals from one or more external devices and (ii) present one or more second control signals to said one or more external devices.
9. The apparatus according to claim 1 , further comprising:
an image capture circuit couple to said first circuit; and
an image display device couple to said second circuit.
10. The apparatus according to claim 1 , wherein said second circuit is further configured to present a compressed bitstream.
11. The apparatus according to claim 1 , wherein said one or more processing parameters of said first circuit comprises one or more parameters selected from the group consisting of exposure parameters, gain parameters, focus parameters, flash parameters and noise reduction parameters.
12. The apparatus according to claim 1 , wherein said encoding related information comprises global picture and region-related statistics.
13. The apparatus to claim 12 , wherein said global picture and region-related statistics comprise one or more types of data selected from the group consisting of size and strengths of regions, texture information, edge information, motion information and color information.
14. The apparatus according to claim 1 , wherein said encoding related information comprises statistics derived from analysis of an encoding process.
15. The apparatus according to claim 14 , wherein said statistics derived from analysis of said encoding process comprise one or more types of data selected from the group consisting of motion vector information and block distortion information.