Semiconductor chip and semiconductor integrated circuit device for relaying a reference clock from one hard macro to another
View Patent ↗A semiconductor chip has: a plurality of hard macros which operates based on a reference clock; and a clock pad through which the reference clock is supplied from the outside to one of the plurality of hard macros. The reference clock supplied to the one hard macro is relayed to other hard macros of the plurality of hard macros in order.
1. A semiconductor chip, comprising:
a plurality of hard macros operating based on a reference clock; and
a clock pad through which said reference clock is supplied from an outside to one of said plurality of hard macros,
wherein said reference clock supplied to said one hard macro is relayed to other hard macros of the plurality of hard macros in order.
2. The semiconductor chip according to claim 1 , further comprising a special interconnection used only for relaying said reference clock,
wherein said plurality of hard macros are connected one after another through said special interconnection.
3. The semiconductor chip according to claim 1 , wherein a power supply line and a ground line for said plurality of hard macros are isolated from a power supply line and a ground line for another logic circuit.
4. The semiconductor chip according to claim 3 , wherein each of said plurality of hard macros includes a PLL circuit which multiplies said reference clock to generate a multiplied reference clock.
5. The semiconductor chip according to claim 4 , wherein each of said plurality of hard macros comprises a SerDes (Serializer/Deserializer) macro.
6. The semiconductor chip according to claim 4 , wherein each of said plurality of hard macros further includes:
an external input buffer configured to receive said reference clock supplied from outside the chip;
a relay input buffer configured to receive said reference clock relayed from another hard macro;
a relay output buffer configured to transfer said reference clock to still another hard macro; and
a selector configured to select any of said external input buffer and said relay input buffer as a selected input buffer and to output said reference clock received from said selected input buffer to said PLL circuit and said relay output buffer.
7. The semiconductor chip according to claim 6 , wherein said plurality of hard macros include a first hard macro and a second macro,
wherein said external input buffer of said first hard macro is connected to said clock pad,
wherein said relay output buffer of said first hard macro is connected to said relay input buffer of said second hard macro,
wherein said selector of said first hard macro selects said external input buffer as said selected input buffer, and
wherein said selector of said second hard macro selects said relay input buffer as said selected input buffer.
8. The semiconductor chip according to claim 4 , wherein each of said plurality of hard macros further includes:
an external input buffer configured to receive said reference clock supplied from outside the chip;
a first relay input buffer and a second relay input buffer configured to receive said reference clock relayed from another hard macro;
a first relay output buffer and a second relay output buffer configured to transfer said reference clock to still another hard macro; and
a selector configured to select any of said external input buffer, said first relay input buffer and said second relay input buffer as a selected input buffer and to output said reference clock received from said selected input buffer to said PLL circuit, said first relay output buffer and said second relay output buffer.
9. The semiconductor chip according to claim 8 , wherein said first relay input buffer receives said reference clock from a first relay input terminal provided on a first side of said each hard macro,
wherein said first relay output buffer outputs said reference clock to a first relay output terminal provided on said first side,
wherein said second relay input buffer receives said reference clock from a second relay input terminal provided on a second side of said each hard macro, and
wherein said second relay output buffer outputs said reference clock to a second relay output terminal provided on said second side.
10. The semiconductor chip according to claim 9 , wherein said first side and said second side face each other.
11. The semiconductor chip according to claim 9 , wherein said plurality of hard macros include:
a first hard macro; and
a second hard macro arranged to be a mirror image of said first hard macro,
wherein said second relay output terminal of said first hard macro is connected to said second relay input terminal of said second hard macro,
wherein and said selector of said second hard macro selects said second relay input buffer as said selected input buffer.
12. The semiconductor chip according to claim 11 , wherein said external input buffer of said first hard macro is connected to said clock pad, and
wherein said selector of said first hard macro selects said external input buffer as said selected input buffer.
13. The semiconductor chip according to claim 3 , further comprising a relay macro having a buffer,
wherein said relay macro is provided between a first hard macro and a second hard macro of said plurality of hard macros,
wherein said buffer supplies said reference clock output from said first hard macro to said second hard macro, and
wherein a power supply line and a ground line for said relay macro is isolated from a power supply line and a ground line for another logic circuit.
14. A semiconductor integrated circuit device, comprising:
a semiconductor chip mounted on a board; and
a clock driver mounted on said board,
wherein said semiconductor chip includes:
a plurality of hard macros operating based on a reference clock; and
a clock pad connected to one of said plurality of hard macros,
wherein said clock driver supplies said reference clock to said clock pad of said semiconductor chip through one reference clock wiring, and
wherein said reference clock supplied to said one hard macro is relayed to other hard macros of the plurality of hard macros in order.
15. The semiconductor integrated circuit device according to claim 14 ,
wherein said semiconductor chip further includes a special interconnection used only for relaying said reference clock, and said plurality of hard macros are connected one after another through said special interconnection.
16. The semiconductor integrated circuit device according to claim 14 , wherein, on said semiconductor chip, a power supply line and a ground line for said plurality of hard macros are isolated from a power supply line and a ground line for another logic circuit.
17. The semiconductor integrated circuit device according to claim 16 , wherein each of said plurality of hard macros includes a PLL circuit which multiplies said reference clock to generate a multiplied reference clock.
18. The semiconductor integrated circuit device according to claim 17 , wherein each of said plurality of hard macros comprises a SerDes (Serializer/Deserializer) macro.