Active inductive load that enhances circuit bandwidth

1. An active load, comprising:

a current source configured to provide a constant bias current;

a first resistive element configured to receive the constant current and provide a bias voltage;

an n-channel metal oxide semiconductor (NMOS) transistor having a gate and a drain, the NMOS transistor configured to receive a drive voltage at the gate, receive the bias voltage between the gate and the drain, provide an output voltage at the drain that is sufficiently different than the drive voltage to maintain headroom, and provide an inductive impedance that enhances circuit bandwidth; and

a second resistive element configured to provide a constant load resistance between the drain and source of the NMOS transistor.

2. The active load of claim 1 , wherein the NMOS transistor includes an internal capacitance and the inductive impedance includes a zero frequency that is based on the internal capacitance and the first resistive element.

3. The active load of claim 2 , wherein the inductive impedance begins increasing at the zero frequency to provide inductive peaking impedance values substantially between the inverse of one of the trans-conductance and the trans-impedance of the NMOS transistor, and a parallel impedance combination including the first resistive element and an internal resistance of the NMOS transistor.

4. The active load of claim 1 , wherein the bias voltage is substantially equal to the threshold voltage of the NMOS transistor.

5. An active load, comprising:

a current source configured to provide a constant bias current;

a first resistive element configured to receive the constant current and provide a bias voltage;

an n-channel metal oxide semiconductor (NMOS) transistor comprising an input and an output, wherein the bias voltage is provided between the input and the output to bias the NMOS transistor, wherein an impedance at the output increases to provide inductive peaking at frequencies higher than a zero frequency that is based on the first resistive element and an internal capacitance of the NMOS transistor; and

a second resistive element coupled to the output of the NMOS transistor and configured to provide a constant load resistance between the drain and source of the NMOS transistor, wherein the impedance at the output rises to a maximum impedance of a parallel combination of the first resistive element, the second resistive element, and an internal resistance of the NMOS transistor.

6. The active load of claim 5 , wherein the impedance at the output increases at frequencies higher than the zero frequency to a value substantially between the inverse of the trans-conductance of the NMOS transistor and the maximum impedance.

7. The active load of claim 5 , wherein the bias voltage is substantially equal to the threshold voltage of the NMOS transistor.

8. The active load of claim 5 , wherein the NMOS transistor is configured to receive a drive voltage at the input and provide an output voltage at the output that is lower than the drive voltage.

9. An active load, comprising:

means for sourcing a constant bias current;

means for providing a bias voltage based on the constant bias current;

means for biasing an n-channel metal oxide semiconductor (NMOS) transistor via the bias voltage to maintain headroom;

means for providing an inductive impedance that enhances circuit bandwidth; and

means for providing a constant load resistance between drain and source of the NMOS transistor.

10. The active load of claim 9 , wherein the means for providing an inductive impedance comprises:

means for providing an inductive impedance that includes a zero frequency based on an internal capacitance of the NMOS transistor and a resistive element.

11. The active load of claim 10 , wherein the means for providing an inductive impedance comprises:

means for providing an inductive impedance that increases at frequencies higher than the zero frequency to provide inductive peaking impedance values substantially between the inverse of the trans-conductance of the NMOS transistor and a parallel impedance combination including the resistive element and an internal resistance of the NMOS transistor.

12. The active load of claim 9 , wherein the means for providing a bias voltage based on the constant bias current comprises:

means for providing a bias voltage that is substantially equal to the threshold voltage of the NMOS transistor.

13. A method for providing an active load, comprising:

sourcing a constant bias current;

providing a bias voltage across a resistive element via the constant bias current;

biasing an n-channel metal oxide semiconductor (NMOS) transistor via the bias voltage to maintain headroom;

providing an inductive impedance to enhance circuit bandwidth; and

providing a constant load resistance between drain and source of the NMOS transistor.

14. The method of claim 13 , wherein providing an inductive impedance comprises:

providing an inductive impedance that includes a zero frequency based on an internal capacitance of the NMOS transistor and the resistive element.

15. The method of claim 14 , wherein providing an inductive impedance comprises:

providing an inductive impedance that increases at frequencies higher than the zero frequency to provide inductive peaking impedance values substantially between the inverse of the trans-conductance of the NMOS transistor and a parallel impedance combination including the resistive element and an internal resistance of the NMOS transistor.

16. The method of claim 13 , wherein providing a bias voltage comprises:

providing a bias voltage that is substantially equal to the threshold voltage of the NMOS transistor.

17. A method for providing an active load, comprising:

sourcing a constant bias current;

receiving the constant bias current at a first resistive element to provide a bias voltage across the first resistive element based on the constant bias current;

biasing an n-channel metal oxide semiconductor (NMOS) transistor via the bias voltage;

outputting at an output of the NMOS transistor an impedance that increases to provide inductive peaking beyond a zero frequency that is based on the first resistive element and an internal capacitance of the NMOS transistor; and

outputting at the output of the NMOS transistor the impedance that rises to a maximum impedance of a parallel combination of the first resistive element, a second resistive element that is coupled to the output and configured to provide a constant load resistance between the drain and source of the NMOS transistor, and an internal resistance of the NMOS transistor.

18. The method of claim 17 , comprising:

outputting at the output of the NMOS transistor the impedance that increases at frequencies higher than the zero frequency to values substantially between the inverse of the trans-conductance of the NMOS transistor and the maximum impedance.

19. The method of claim 17 , wherein biasing an NMOS transistor comprises:

biasing via the bias voltage which is substantially equal to a threshold voltage of the NMOS transistor.

20. The method of claim 17 , comprising:

receiving a drive voltage at an input of the NMOS transistor; and

outputting an output voltage at the output that is lower than the drive voltage.