Pulse width modulation circuit and multiphase clock generation circuit
View Patent ↗A pulse width modulation circuit comprises a multiphase clock generation section which generates multiphase clock signals based on a reference clock, and a pulse width modulation signal generation section which generates pulse width modulation signals based on input data and on multiphase clock signals generated by the multiphase clock generation section. The multiphase clock generation section has a phase-locked loop circuit and a clock selection circuit which selects an arbitrary clock signal from among the multiphase clock signals and outputs the selected clock signal to the phase-locked loop circuit as a feedback clock.
1. A pulse width modulation circuit, comprising:
a multiphase clock generation section which generates multiphase clock signals based on a reference clock; and
a pulse width modulation signal generation section which generates pulse width modulation signals based on input data and on multiphase clock signals generated by the multiphase clock generation section,
wherein the multiphase clock generation section includes a phase-locked loop circuit and a clock selection circuit which selects an arbitrary clock signal from among the multiphase clock signals and outputs the selected clock signal to the phase-locked loop circuit as a feedback clock.
2. The pulse width modulation circuit according to claim 1 , wherein a phase interpolation circuit is provided in the multiphase clock generation section in a stage after a voltage-controlled oscillator included in the phase-locked loop circuit, and output signals from the phase interpolation circuit are output as multiphase clock signals.
3. The pulse width modulation circuit according to claim 1 , wherein the clock selection circuit includes a first selector which selects an arbitrary clock signal from among the multiphase clock signals generated by the multiphase clock generation section, a second selector which selects a clock signal different in phase from the clock signal selected by the first selector, and a gate circuit which outputs the final selected clock based on the clock signal selected by the first selector and the clock signal selected by the second selector.
4. The pulse width modulation circuit according to claim 3 , wherein the second selector includes a shifting section which shifts the clock signal selected by the first selector.
5. The pulse width modulation circuit according to claim 3 , wherein the clock selection circuit includes a control circuit which sets the clock signals selected by the first selector and by the second selector.
6. The pulse width modulation circuit according to claim 1 , wherein the pulse width modulation signals comprise signals used to modulate laser output.
7. The pulse width modulation circuit according to claim 1 , wherein the clock selection circuit comprises a computation circuit which performs computation to determine the feedback clock every fixed period of the reference clock.
8. The pulse width modulation circuit according to claim 7 , wherein the clock selection circuit further comprises a register which holds the computation results, and the computation to determine the feedback clock comprises a computation to determine the clock to select by addition or subtraction of a prescribed value to or from a value held in the register.
9. The pulse width modulation circuit according to claim 7 , wherein the clock selection circuit comprises:
a register holding the computation result;
an oscillation frequency general adjustment circuit periodically adding or subtracting a general frequency adjustment value to or from the computation result, and renewing the computation result; and
an oscillation frequency fine adjustment circuit periodically adding or subtracting a fine frequency adjustment value to or from the computation result within a fine adjustment period.
10. The pulse width modulation circuit according to claim 9 , wherein the oscillation frequency fine adjustment circuit comprises:
a counter counting the reference clock; and
a comparison circuit comparing a count value of the counter with a predetermined fine adjustment period setting value,
wherein the fine adjustment period is determined by comparing a result of the comparison circuit.
11. A multiphase clock generation circuit, comprising:
a phase comparator, which compares a reference clock and a feedback clock and outputs a phase difference signal according to the comparison result;
a multiphase clock generation section, which controls an oscillation frequency based on the phase difference signal and generates multiphase clock signals; and,
a clock selection circuit, which performs computation to select the feedback clock from among the multiphase clock signals every fixed period of the reference clock, and switches the feedback clock based on the computation result.
12. The multiphase clock generation circuit according to claim 11 , wherein the clock selection circuit comprises a selected clock number holding register which holds the computation result, and a computation circuit which, for each fixed period of the reference clock, adds or subtracts a frequency variable width setting value, set in advance, to or from a value held in the register.
13. The multiphase clock generation circuit according to claim 11 , wherein the clock selection circuit comprises a clock switching circuit which switches, among rising and falling edges of the feedback clock, the feedback clock at the edge on which comparison with the reference clock by the phase comparator is not performed.
14. The multiphase clock generation circuit according to claim 11 , wherein the clock selection circuit comprises:
a register holding the computation result;
an oscillation frequency general adjustment circuit periodically adding or subtracting a general frequency adjustment value to or from the computation result, and renewing the computation result; and
an oscillation frequency fine adjustment circuit periodically adding or subtracting a fine frequency adjustment value to or from the computation result within a fine adjustment period.
15. The multiphase clock generation circuit according to claim 14 , wherein the oscillation frequency fine adjustment circuit comprises:
a counter counting the reference clock; and
a comparison circuit comparing a count value of the counter with a predetermined fine adjustment period setting value,
wherein the fine adjustment period is determined by comparing result of the comparison circuit.
16. The multiphase clock generation circuit according to claim 11 , wherein the clock selection circuit comprises a general adjusting means for generally adjusting the oscillation frequency and a fine adjusting means for precisely adjusting the oscillation frequency.
17. The multiphase clock generation circuit according to claim 16 , wherein the general adjusting means adds or subtracts a general frequency adjustment value to or from the computation result and renews the computation result, and
wherein the fine adjusting means further adds or subtracts a fine adjustment value thereto or therefrom within a fine adjustment period.