Clock generation circuit
A clock generation circuit includes a phase comparator inputted with a reference clock and a feedback clock, a current controlled oscillator for generating a clock frequency according to an output of the phase comparator, a frequency dividing circuit for dividing the clock frequency by a frequency dividing rate based on a frequency dividing rate setting signal to produce a feedback clock, and a control circuit for counting the clock frequency and outputting a control current setting signal that sets a control current of the current controlled oscillator and the frequency dividing rate setting signal based on a count value.
1 . A clock generation circuit comprising:
a phase comparator inputted with a reference clock and a feedback clock;
a current controlled oscillator for generating an operation clock according to an output of the phase comparator;
a first modulation unit for counting the operation clock and changing a frequency dividing rate of the feedback clock inputted to the phase comparator according to a count value; and
a second modulation unit for counting the operation clock and for changing a control current of the current controlled oscillator according to a count value.
2 . A clock generation circuit comprising:
a phase comparator inputted with a reference clock and a feedback clock;
a current controlled oscillator for generating an operation clock based on an output from the phase comparator;
a frequency dividing circuit for dividing the operation clock by a frequency dividing rate based on a frequency dividing rate setting signal to produce the feedback clock; and
a control circuit for counting the operation clock and outputting a control current setting signal that sets a control current of the current controlled oscillator and the frequency dividing rate setting signal based on a count value.
3 . The clock generation circuit according to claim 2 , wherein the control circuit comprising:
a first setting circuit for counting the operation clock and outputting the control current setting signal; and
a frequency dividing rate setting circuit for counting the operation clock and outputting the control frequency dividing rate setting signal.
4 . The clock generation circuit according to claim 2 , further comprising a D/A converter for generating a current having a current value based on the control current setting signal.
5 . The clock generation circuit according to claim 3 , wherein the control circuit counts the feedback clock, and further includes a counter for outputting a reset signal to the first setting circuit and a frequency rate setting circuit based on a count value.
6 . The clock generation circuit according to claim 5 , wherein the count value for the counter to output a reset signal is determined according to a cycle that changes a control current of the current controlled oscillator.