Methods of fabricating contact regions for FET incorporating SiGe
Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and/or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography.
1 - 36 . (canceled)
37 . A method of fabricating contact regions for a FET, the method comprising:
providing a substrate comprising at least one of Si, SiGe, and Ge;
providing a gate stack disposed above the substrate, the gate stack defining a channel region disposed thereunder,
epitaxially depositing a SiGe layer in at least one area of the substrate adjacent to the gate stack, the SiGe layer being at least partially relaxed by the introduction of crystalline defects therein;
providing a metal layer over the SiGe layer; and
reacting the metal layer with the SiGe layer to form a region comprising at least one of silicide and silicide/germanicide.
38 . The method of claim 37 wherein the metal layer comprises Ti or Co.
39 . The method of claim 37 wherein the metal layer comprises Ni.
40 . The method of claim 37 wherein the channel region comprises a strained semiconductor material.
41 . The method of claim 40 wherein the strained semiconductor material comprises SiGe or Ge.
42 . The method of claim 40 wherein the strained semiconductor material comprises Si.
43 . The method of claim 37 , wherein the step of reacting the metal layer with the SiGe layer comprises thermal annealing.
44 . The method of claim 37 , wherein an average surface roughness of the channel region is less than approximately 2 nm.
45 . The method of claim 44 , wherein the surface roughness is less than approximately 0.77 nm.
46 . The method of claim 37 , wherein the crystalline defects substantially do not propagate into the channel region from the SiGe layer.
47 . The method of claim 37 , wherein the substrate has a first Ge concentration and the SiGe layer has a second Ge concentration exceeding the first Ge concentration.
48 . The method of claim 37 , further comprising forming a shallow trench isolation region such that the region comprising at least one of silicide and silicide/germanicide is disposed proximate to the shallow trench isolation region.
49 . A method of fabricating contact regions for a FET, the method comprising:
providing a substrate comprising at least one of Si, SiGe, and Ge;
providing a gate stack disposed above the substrate, the gate stack defining a channel region disposed thereunder, the channel region comprising a strained semiconductor material;
epitaxially depositing a strained SiGe layer in at least one area of the substrate adjacent to the gate stack;
providing a metal layer over the strained SiGe layer; and
reacting the metal layer with the SiGe layer to form a region comprising at least one of silicide and silicide/germanicide.
50 . The method of claim 49 wherein the metal layer comprises Ti or Co.
51 . The method of claim 49 wherein the metal layer comprises Ni.
52 . The method of claim 49 wherein the strained semiconductor material comprises SiGe or Ge.
53 . The method of claim 49 wherein the strained semiconductor material comprises Si.
54 . The method of claim 49 , wherein an average surface roughness of the channel region is less than approximately 2 nm.
55 . The method of claim 54 , wherein the surface roughness is less than approximately 0.77 nm.
56 . The method of claim 49 , wherein the substrate has a first Ge concentration and the SiGe layer has a second Ge concentration exceeding the first Ge concentration.