Memory circuit with automatic refresh function
View Patent ↗According to the present invention, a memory circuit requiring refresh operations a first circuit which receives a command in synchronization with a clock signal, and which generates a first internal command internally and a second circuit which generates a second internal command, e.g., a refresh command, internally in a prescribed refresh cycle. And an internal circuit, according to said first internal command, executes corresponding control through clock-synchronous operations, and when said refresh command is issued, sequentially executes control corresponding to the refresh command and control corresponding to said first internal command through clock-asynchronous operations. According to the present invention, when a refresh timing signal is generated, the refresh operation can be intrupted among the external command operations.
1. A memory circuit requiring refresh operations, comprising:
a memory core having memory cells;
a first circuit which receives a command supplied in synchronization with an external clock signal, and which generates a first internal command internally;
a second circuit which generates a refresh command internally in a prescribed refresh cycle which is larger than the cycle of said external clock signal; and
a memory control circuit which has a first internal operation cycle and a second internal operation cycle shorter than said first internal operation cycle, executes control corresponding to said first internal command according to the first internal operation cycle, and when said refresh command is issued, executes a control corresponding to the refresh command and a control corresponding to said first internal command, sequentially, according to the second internal operation cycle.
2. The memory circuit according to the claim 1 , wherein
the memory control circuit executes the corresponding control according to the first internal operation cycle while a finish timing of the internal operation is earlier than a generation timing of the first internal command or the refresh command, whereas, executes the corresponding control according to the second internal operation cycle while the generation timing of the first internal command or the refresh command is earlier than the finish timing of the internal operation.