IP Library Granted Patent US 7,373,461
Granted Patent B2
US 7,373,461 · App. 11/413,244 · Granted May 13, 2008

Speculative directory lookup for sharing classification

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Quick Facts
Patent No.
US 7,373,461
App. No.
11/413,244
Granted
May 13, 2008
Kind
B2
Abstract

In one embodiment, a node for a multi-node computer system comprises a coherence directory configured to store coherence states for coherence units in a local memory of the node and a coherence controller configured to receive a coherence request for a requested coherence unit. The requested coherence unit is included in a memory region that includes at least two coherence units, and the coherence controller is configured to read coherence states corresponding to two or more coherence units from the coherence directory responsive to the coherence request. The two or more coherence units are included in a previously-accessed memory region, and the coherence controller is configured to provide the requested coherence unit with a predicted coherence state responsive to the coherence states in the previously accessed memory region.

Claims (27)

1. A node for a multi-node computer system, the node comprising:

a coherence directory configured to store coherence states for coherence units in a local memory of the node; and

a coherence controller configured to receive a coherence request for a requested coherence unit, wherein the requested coherence unit is included in a memory region that includes at least two coherence units, and wherein the coherence controller is configured to read coherence states corresponding to two or more coherence units from the coherence directory responsive to the coherence request, wherein the two or more coherence units are included in a previously-accessed memory region, and wherein the coherence controller is configured to provide the requested coherence unit with a predicted coherence state responsive to the coherence states in the previously accessed memory region.

2. The node as recited in claim 1 wherein the coherence controller comprises hardware circuitry configured to access the coherence directory.

3. The node as recited in claim 1 wherein the coherence controller comprises coherence code executable on a processor in the node.

4. The node as recited in claim 1 wherein the coherence controller is configured to predict coherence states for one or more additional coherence units in the memory region, and to provide the additional coherence units in response to the coherence request.

5. The node as recited in claim 1 wherein the predicted coherence state comprises a maximum permission between the coherence request and a coherence state indicated by the previously-accessed memory region.

6. The node as recited in claim 1 wherein the coherence controller is configured to predict the predicted coherence state responsive to a stability corresponding to the previously accessed memory region.

7. The node as recited in claim 6 wherein the stability measure comprises a number of iterations of a coherence state pattern in previously-accessed memory regions.

8. The node as recited in claim 1 wherein the read is speculative.

9. The node as recited in claim 1 wherein the coherence controller is configured to track the previously accessed memory regions responsive to a program counter of an instruction causing the coherence request.

10. A method comprising:

receiving a coherence request for a requested coherence unit in a node, wherein the node comprises a coherence directory configured to store coherence states for coherence units in a local memory of the node, and wherein the requested coherence unit is included in a memory region that includes at least two coherence units;

reading coherence states corresponding to two or more coherence units from the coherence directory responsive to the coherence request, wherein the two or more coherence units are included in a previously-accessed memory region; and

providing the requested coherence unit with a predicted coherence state responsive to the coherence states in the previously accessed memory region.

11. The method as recited in claim 10 further comprising:

predicting coherence states for one or more additional coherence units in the memory region; and

providing the additional coherence units in response to the coherence request.

12. The method as recited in claim 10 wherein the predicted coherence state comprises a maximum permission between the coherence request and a coherence state indicated by the previously-accessed memory region.

13. The method as recited in claim 10 further comprising predicting the predicted coherence state responsive to a stability corresponding to the previously accessed memory region.

14. The method as recited in claim 13 wherein the stability measure comprises a number of iterations of a coherence state pattern in previously-accessed memory regions.

15. The method as recited in claim 10 wherein the reading is speculative.

16. The method as recited in claim 10 further comprising tracking the previously accessed memory regions responsive to a program counter of an instruction causing the coherence request.

17. A system comprising a plurality of nodes coupled to an interconnect, wherein a first node of the plurality of nodes is configured to generate a coherence request for a requested coherence unit for which a second node of the plurality of nodes is the home node, and wherein the second node comprises a local memory and a coherence directory configured to store coherence states for coherence units in the local memory, and wherein the requested coherence unit is included in a memory region that includes at least two coherence units, and wherein the second node is configured to read coherence states corresponding to two or more coherence units from the coherence directory responsive to the coherence request, wherein the two or more coherence units are included in a previously-accessed memory region, and wherein the second node is configured to provide the requested coherence unit with a predicted coherence state responsive to the coherence states in the previously accessed memory region.

18. The system as recited in claim 17 wherein second node is configured to predict coherence states for one or more additional coherence units in the memory region, and to provide the additional coherence units in response to the coherence request.

19. The system as recited in claim 17 wherein the second node is configured to predict the predicted coherence state responsive to a stability corresponding to the previously accessed memory region.

20. The system as recited in claim 17 wherein the read is speculative.

Assignments (2)
MERGER AND CHANGE OF NAME Recorded Dec 16, 2015
From: ORACLE USA, INC.; SUN MICROSYSTEMS, INC.; ORACLE AMERICA, INC.
To: ORACLE AMERICA, INC.
Reel/Frame 037303/0025 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 28, 2006
From: ZEFFER, HAKAN E.; HAGERSTEN, ERIK E.
To: SUN MICROSYSTEMS, INC.
Reel/Frame 017836/0845 →