Low noise microwave frequency synthesizer having fast switching

1. A frequency synthesizer, comprising:

an accumulator for accumulating a first seed word, said first seed word based on a desired output frequency, at a high variable clock rate starting from a remainder word for updating a reference word at an output of the accumulator at said high variable clock rate, said reference word having a most significant bit (MSB) and less significant bits (LSB)s, said remainder word corresponding to said LSBs at overflows of said MSB;

a tracking filter for receiving an MSB signal, said MSB signal corresponding to changes in said MSB, and issuing a filtered output signal having an actual output frequency based on a frequency of said MSB signal; and

a variable rate clock generator for providing said high variable clock rate at a combination of at least one fixed clock rate and a clock interpolation rate, said clock interpolation rate responsive to a second seed word, said second seed word based on said desired output frequency.

2. The frequency synthesizer of claim 1 , wherein:

the variable rate clock generator includes a clock rate interpolator using said second seed word for generating a baseband variable clock signal at a clock interpolation rate, and a single sideband (SSB) upconverter using at least one fixed clock signal having a fixed clock rate for frequency upconverting said baseband variable clock signal to a single sideband (SSB) variable clock signal having an SSB variable clock rate differing from said fixed clock rate by said clock interpolation rate.

3. The frequency synthesizer of claim 2 , wherein:

said clock rate interpolator includes an IQ direct digital synthesizer using said second seed word for synthesizing said baseband variable clock signal as an IQ variable clock signal at said clock interpolation rate; and said SSB upconverter includes an IQ modulator for IQ modulating said fixed clock signal with said IQ variable clock signal for providing said SSB variable clock signal.

4. The frequency synthesizer of claim 3 , wherein:

said SSB variable clock rate is said high variable clock rate.

5. The frequency synthesizer of claim 3 , wherein:

said SSB upconverter includes said IQ modulator for modulating an intermediate said fixed clock signal having an intermediate said fixed clock rate with said IQ variable clock signal for providing said SSB variable clock signal; and a high offset upconverter using an offset high said fixed clock signal at an offset high said fixed clock rate for frequency upconverting said SSB variable clock signal to a high variable clock signal having said high variable clock rate, said high variable clock rate differing from a combination of said intermediate fixed clock rate and said offset high fixed clock rate by said clock interpolation rate.

6. The frequency synthesizer of claim 3 , wherein:

said IQ modulator includes a scalar detector for detecting scalar amplitudes of said SSB variable clock signal; and a suppression algorithm for using said scalar amplitudes for controlling compensation circuitry for suppressing signals having rates other than said SSB variable clock rate.

7. The frequency synthesizer of claim 6 , wherein:

said compensation circuitry includes a carrier leak compensator for suppressing feedthrough of said fixed clock signal into said SSB variable clock signal, and quadrature and ratio adjusters for suppressing double sideband conversion of said baseband variable clock signal to said SSB variable clock signal.

8. A frequency synthesizer, comprising:

an accumulator for accumulating a first seed word at a high variable clock rate starting from a remainder word for updating a reference word at an output of the accumulator at said high variable clock rate, said reference word having a most significant bit (MSB) and less significant bits (LSB)s, said remainder word corresponding to said LSBs at overflows of said MSB;

a tracking filter for receiving an MSB signal, said MSB signal corresponding to changes in said MSB, and issuing a filtered output signal having an actual output frequency based on a frequency of said MSB signal; and

a seed calculator for providing said first seed word based on a desired output frequency.

9. The frequency synthesizer of claim 8 , wherein:

the accumulator operates according to a modulus of the accumulator for providing said MSB; and

said first seed word is generated according to:

K =integer{[( F out/ C )*(2 M /Fhclk )+Δ K/ 2]/Δ K}*ΔK

where K is said first seed word as an integer; ΔK is an incremental resolution of said first seed word K; Fhclk is a high fixed clock rate of one fixed clock rate or a combination of fixed clock rates; 2 M is said accumulator modulus; Fout is said desired output frequency; and C is a frequency ratio of said actual output frequency to said MSB signal frequency.

10. The frequency synthesizer of claim 8 , further comprising:

a variable rate clock generator for providing said high variable clock rate differing from a high fixed clock rate by a clock interpolation rate, where said high fixed clock rate is one fixed clock rate or a combination of fixed clock rates; wherein

the variable rate clock generator includes a direct digital synthesizer for synthesizing said clock interpolation rate from a second seed word, and

the seed calculator is a dual seed calculator for providing said second seed word based on said first seed word and said desired output frequency.

11. The frequency synthesizer of claim 10 , wherein:

said direct digital synthesizer uses a direct digital synthesis (dds) fixed clock rate and a dds modulus for providing said clock interpolation rate; and

said second seed word is generated according to:

L =[( F out/ C* 2 M /K )− Fhclk ](2 Mb /Fdclk )

where L is said second seed word; Fout is said desired output frequency; K is said first seed word; Fhclk is said high fixed clock rate; the 2 M is a modulus of the accumulator; the 2 Mb is said dds modulus; the Fdclk is said dds fixed clock rate; and C is a frequency ratio of said actual output frequency to said MSB signal frequency.

12. The frequency synthesizer of claim 8 , further comprising:

a variable rate clock generator including a clock rate interpolator for generating said clock interpolation rate from a second seed word, said second seed word based on said desired output frequency, and a frequency upconverter for using at least one fixed clock rate for frequency upconverting said clock interpolation rate to said high variable clock rate.

13. The frequency synthesizer of claim 12 , wherein:

said frequency upconverter includes an IQ modulator for IQ modulating a fixed clock signal having said fixed clock rate with a baseband variable clock signal having said clock interpolation rate for providing a single sideband (SSB) variable clock signal having an SSB variable clock rate differing from said fixed clock rate by said interpolation clock rate and using said SSB variable clock signal for providing a high variable clock signal at said high variable clock rate.

14. A method for synthesizing a frequency, comprising:

accumulating a first seed word, said first seed word based on a desired output frequency, at a high variable clock rate starting from a remainder word for updating a reference word at an output of an accumulator at said high variable clock rate, said reference word having a most significant bit (MSB) and less significant bits (LSB)s;

retaining said LSBs at overflows of said MSB as said remainder word;

issuing an MSB signal corresponding to changes in said MSB;

providing a filtered output signal having an actual output frequency based on a frequency of said MSB signal; and

generating said high variable clock rate at a combination of at least one fixed clock rate and a clock interpolation rate, said clock interpolation rate responsive to a second seed word, said second seed word based on said desired output frequency.

15. The method of claim 14 , wherein:

providing said filtered output signal includes controlling said actual output frequency according to a phase difference between a phase of said MSB signal and a phase derived from said output signal.

16. The method of claim 15 , wherein:

providing said filtered output signal further includes dividing said actual output frequency by a divide factor for providing said actual output frequency at said MSB signal frequency multiplied by said divide factor.

17. The method of claim 14 , further comprising:

generating a baseband variable clock signal at a clock interpolation rate based on said second seed word; and

using at least one fixed clock signal having a fixed clock rate for frequency upconverting said baseband variable clock signal to a single sideband (SSB) variable clock signal having an SSB variable clock rate differing from said fixed clock rate by said clock interpolation rate.

18. The method of claim 17 , wherein:

generating said baseband variable clock signal includes using said second seed word for synthesizing said baseband variable clock signal as an IQ variable clock signal having said clock interpolation rate; and

frequency upconverting said baseband variable clock signal includes IQ modulating said fixed clock signal with said IQ variable clock signal for providing said SSB variable clock signal.

19. The method of claim 17 , wherein:

said SSB variable clock rate is said high variable clock rate.

20. The method of claim 18 , wherein:

frequency upconverting said baseband variable clock signal includes IQ modulating an intermediate said fixed clock signal having an intermediate fixed clock rate with said IQ variable clock signal for providing said SSB variable clock signal, and using an offset high said fixed clock signal at an offset high fixed clock rate for frequency upconverting said SSB variable clock signal to a high variable clock signal having said high variable clock rate differing from a combination of said intermediate fixed clock rate and said offset high fixed clock rate by said clock interpolation rate.

21. The method of claim 18 , further comprising:

detecting scalar amplitudes of said SSB variable clock signal; and

using said scalar amplitudes for suppressing signals having rates other than said SSB variable clock rate.

22. The method of claim 21 , wherein:

suppressing signals includes suppressing feedthrough of said fixed clock signal into said SSB variable clock signal, and suppressing double sideband conversion from said baseband variable clock signal to said SSB variable clock signal.

23. A method for synthesizing a frequency, comprising:

accumulating a first seed word at a high variable clock rate starting from a remainder word for updating a reference word at an output of an accumulator at said high variable clock rate, said reference word having a most significant bit (MSB) and less significant bits (LSB)s;

retaining said LSBs at overflows of said MSB as said remainder word;

issuing an MSB signal corresponding to changes in said MSB;

providing a filtered output signal having an actual output frequency based on a frequency of said MSB signal; and

generating said first seed word based on a desired said output frequency.

24. The method of claim 23 , wherein:

accumulating said first seed word includes operating according to a modulus of the accumulator for providing said MSB; and

said first seed word is generated according to:

K =integer{[( F out/ C )*(2 M /Fhclk )+Δ K/ 2]/Δ K}*ΔK

where K is said first seed word as an integer; ΔK is an incremental resolution of said first seed word K; Fhclk is a high fixed clock rate at one fixed clock rate or a combination of fixed clock rates; 2 M is said accumulator modulus; Fout is said desired output frequency; and C is a frequency ratio of said desired output frequency Fout to said MSB signal frequency.

25. The method of claim 23 , further comprising:

generating said high variable clock rate at a combination of a high fixed clock rate and a clock interpolation rate, where said high fixed clock rate is one fixed clock rate or a combination of fixed clock rates;

synthesizing said clock interpolation rate from a second seed word; and

generating said second seed word based on said first seed word and said desired output frequency.

26. The method of claim 25 , wherein:

generating said second seed word is further based on a direct digital synthesis (dds) fixed clock rate and a dds modulus according to:

L =[( F out/ C* 2 M /K )− Fhclk ](2 Mb /Fdclk )

where L is said second seed word; Fout is said desired output frequency; K is said first seed word; Fhclk is said high fixed clock rate; the 2 M is a modulus of the accumulator; the 2 Mb is said dds modulus; the Fdclk is said dds fixed clock rate; and C is a frequency ratio of said desired output frequency Fout to said MSB signal frequency.

27. The method of claim 23 , further comprising:

generating a clock interpolation rate from a second seed word, said second seed word based on said desired output frequency; and

using at least one fixed clock rate for frequency upconverting said clock interpolation rate to said high variable clock rate.

28. The method of claim 27 , wherein:

IQ modulating a fixed clock signal having said fixed clock rate with a baseband variable clock signal having said clock interpolation rate for providing a single sideband (SSB) variable clock signal having an SSB variable clock rate differing from said fixed clock rate by said interpolation clock rate; and

using said SSB variable clock signal for providing a high variable clock signal at said high variable clock rate.