Power semiconductor and method of fabrication
This invention is generally concerned with power semiconductors such as power MOS transistors, insulated gate by bipolar transistors (IGBTs), high voltage diodes and the like, and method for their fabrication. A power semiconductor, the semiconductor comprising a power device, said power device having first and second electrical contact regions and a drift region extending therebetween; and a semiconductor substrate mounting said device; and wherein said power semiconductor includes an electrically insulating layer between said semiconductor substrate and said power device, said electrically insulating layer having a thickness of at least 5 μm.
1. A method of fabricating a power semiconductor, the method comprising:
forming a semiconductor device on a semiconductor-on-insulator (SOI) substrate, said SOI substrate comprising a first substrate, an intermediate insulating layer and a semiconducting layer;
forming one or more at least partially insulating layers comprising metallization layers over said semiconductor device;
attaching a second substrate on top of said one or more at least partially insulating layers;
removing said first substrate;
forming an at least partially insulating layer under said intermediate insulating layer; and
etching through said at least partially insulating layer and said intermediate insulating layer to make connections to said device.
2. A method as claimed in claim 1 wherein said one or more at least partially insulating layers have a thickness of greater than 10 μm.
3. A method as claimed in claim 1 wherein said attaching of said second substrate comprises wafer bonding.
4. A method as claimed in claim 1 wherein said one or more at least partially insulating layers have a thickness of greater than 15 μm.
5. A method of fabricating a power semiconductor having a drift region such that said drift region is spaced away from a substrate of said power semiconductor by at least 5 μm, the method comprising:
forming a power semiconductor device on a semiconductor-on-insulator (SOI) substrate, said SOI substrate comprising a first substrate, an intermediate insulating layer and a semiconducting layer;
forming a plurality of at least partially insulating layers over said power semiconductor device, said plurality of at least partially insulating layers having a thickness of at least 5 μm;
wafer bonding a second substrate on top of said plurality of at least partially insulating layers;
removing said first substrate such that said power semiconductor device is supported by said second substrate; and
forming a heat sink for said device by forming metallization within said plurality of at least partially insulating layers, said metallization extending from a contact of said power semiconductor device through multiple layers of said plurality of at least partially insulating layers towards said second substrate to enhance thermal conduction from said power semiconductor device to said second substrate.
6. A method as claimed in claim 5 wherein said forming of said heat sink comprises forming said metallization to extend into a said at least partially insulating layer adjacent said second substrate.
7. A method as claimed in claim 6 further comprising electrically insulating said power semiconductor device from said second substrate and said metallization using said at least partially insulating layer adjacent said second substrate, and forming connections to said power semiconductor device through said intermediate insulating layer, said intermediate insulating layer being on an opposite side of said power semiconductor device to said metallization.
8. A method as claimed in claim 6 wherein said forming of said heat sink comprises forming said metallization to extend to form an electrical contract with said second substrate, the method further comprising using said second substrate for a first external electrical contact to said power semiconductor and forming at least one further external connection for said power semiconductor device through said intermediate insulating layer, said intermediate insulating layer being on an opposite side of said power semiconductor device to said metallization.
9. A method as claimed in claim 5 wherein said forming of said heat sink comprises forming said metallization to extend from a plurality of contact regions of said power semiconductor device.
10. A method as claimed in claim 5 wherein said forming of said heat sink comprises forming fins using said metallization.
11. A method as claimed in claim 5 wherein said plurality of at least partially insulating layers have a thickness of at least 10 μm.
12. A method as claimed in claim 5 wherein said plurality of at least partially insulating layers have a thickness of at least 15 μm.