Frequency modulation linearization system for a Fractional-N offset PLL
View Patent ↗A linearization system is provided for a Fractional-N Offset Phase Locked Loop (FN-OPLL) in a frequency or phase modulation system. In general, the linearization system processes a modulation signal to provide a linearized modulation signal to a fractional-N divider in a reference path of the FN-OPLL such that a frequency or phase modulation component at the output of the FN-OPLL is substantially linear with respect to the modulation signal.
1. A frequency synthesizer comprising:
combiner circuitry adapted to combine an initial fractional divide value and a linearized modulation signal to provide a combined fractional divide value;
a fractional-N divider adapted to fractionally divide a reference signal based on the combined fractional divide value to provide a divided reference signal;
loop circuitry adapted to provide an output signal based on the divided reference signal and a feedback signal;
feedback circuitry adapted to provide the feedback signal based on mixing the output signal and a local oscillator signal;
second frequency synthesizer circuitry adapted to provide the local oscillator signal based on a control value; and
linearization circuitry adapted to process a modulation signal to provide the linearized modulation signal such that a modulation component of the output signal has a substantially linear relationship to the modulation signal.
2. The frequency synthesizer of claim 1 wherein the linearization circuitry is further adapted to provide the linearized modulation signal based on the equation:
Δ
N
FN
-
OPLL
=
-
N
2
Δ
N
PLL
-
N
2
N
0
-
N
0
,
wherein ΔN FN-OPLL is the linearized modulation signal, ΔN PLL is the modulation signal, N 0 is the initial fractional divide value, and N 2 is the control value.
3. The frequency synthesizer of claim 1 wherein the linearization circuitry is further adapted to provide the linearized modulation signal based on an approximation of the equation:
Δ
N
FN
-
OPLL
=
-
N
2
Δ
N
PLL
-
N
2
N
0
-
N
0
,
wherein ΔN FN-OPLL is the linearized modulation signal, ΔN PLL is the modulation signal, N 0 is the initial fractional divide value, and N 2 is the control value.
4. The frequency synthesizer of claim 1 wherein the linearization circuitry is further adapted to provide the linearized modulation signal based on a number of terms selected from the equation:
Δ
N
FN
-
OPLL
=
N
0
∑
k
=
1
∞
(
N
0
N
2
Δ
N
PLL
)
k
wherein ΔN FN-OPLL is the linearized modulation signal, ΔN PLL is the modulation signal, N 0 is the initial fractional divide value, and N 2 is the control value.
5. The frequency synthesizer of claim 1 wherein the linearization circuitry is further adapted to provide the linearized modulation signal based on the equation:
Δ
N
FN
-
OPLL
=
N
0
[
(
N
0
N
2
Δ
N
PLL
)
+
(
N
0
N
2
Δ
N
PLL
)
2
]
wherein ΔN FN-OPLL is the linearized modulation signal, ΔN PLL is the modulation signal, N 0 is the initial fractional divide value, and N 2 is the control value.
6. The frequency synthesizer of claim 1 wherein the linearization circuitry is further adapted to provide the linearized modulation signal based on the equation:
Δ
N
FN
-
OPLL
=
N
2
Δ
N
PLL
N
2
N
0
-
N
0
,
wherein ΔN FN-OPLL is the linearized modulation signal, ΔN PLL is the modulation signal, N 0 is the initial fractional divide value, and N 2 is the control value.
7. The frequency synthesizer of claim 1 wherein the linearization circuitry is further adapted to provide the linearized modulation signal based on an approximation of the equation:
Δ
N
FN
-
OPLL
=
N
2
Δ
N
PLL
+
N
2
N
0
-
N
0
,
wherein ΔN FN-OPLL is the linearized modulation signal, ΔN PLL is the modulation signal, N 0 is the initial fractional divide value, and N 2 is the control value.
8. The frequency synthesizer of claim 1 wherein the linearization circuitry is further adapted to provide the linearized modulation signal based on a number of terms selected from the equation:
Δ
N
FN
-
OPLL
=
N
0
∑
k
=
1
∞
(
-
N
0
N
2
Δ
N
PLL
)
k
wherein ΔN FN-OPLL is the linearized modulation signal, ΔN PLL is the modulation signal, N 0 is the initial fractional divide value, and N 2 is the control value.
9. The frequency synthesizer of claim 1 wherein the linearization circuitry is further adapted to provide the linearized modulation signal based on the equation:
Δ
N
FN
-
OPLL
=
N
0
[
(
-
N
0
N
2
Δ
N
PLL
)
+
(
-
N
0
N
2
Δ
N
PLL
)
2
]
wherein ΔN FN-OPLL is the linearized modulation signal, ΔN PLL is the modulation signal, N 0 is the initial fractional divide value, and N 2 is the control value.
10. The frequency synthesizer of claim 1 wherein the loop circuitry comprises:
a phase detector adapted to compare a phase of the divided reference signal to a phase of the feedback signal;
a loop filter adapted to filter an output of the phase detector to provide a control signal; and
controlled oscillator circuitry adapted to provide the output signal based on the control signal.
11. The frequency synthesizer of claim 10 wherein the feedback circuitry comprises mixer circuitry adapted to multiply the output signal and the local oscillator signal to provide the feedback signal.
12. The frequency synthesizer of claim 11 wherein the feedback circuitry further comprises filtering circuitry adapted to filter the feedback signal prior to providing the feedback signal to the phase detector.
13. The frequency synthesizer of claim 1 wherein the second frequency synthesizer circuitry comprises a phase locked loop (PLL) and the control value is a second fractional divide value, such that the initial fractional divide value and the second fractional divide value are provided to control a center frequency of the output signal.
14. The frequency synthesizer of claim 1 wherein an output of the second frequency synthesizer circuitry is coupled to an input of the fractional-N divider to provide the reference signal.
15. The frequency synthesizer of claim 1 wherein the combiner circuitry has a digital interface and the linearized modulation signal is a digital signal.
16. The frequency synthesizer of claim 15 wherein the frequency synthesizer is part of modulation circuitry in a transmitter of a mobile terminal and the modulation circuitry provides an all digital path from processing circuitry of the mobile terminal to the digital interface of the combiner circuitry.
17. A method comprising:
combining an initial fractional divide value and a linearized modulation signal to provide a combined fractional divide value;
fractionally dividing a reference signal based on the combined fractional divide value to provide a divided reference signal;
providing an output signal based on the divided reference signal and a feedback signal;
providing the feedback signal based on mixing the output signal and a local oscillator signal;
providing the local oscillator signal based on a control value; and
processing a modulation signal to provide the linearized modulation signal such that a modulation component of the output signal has a substantially linear relationship to the modulation signal.
18. The method of claim 17 wherein processing the modulation signal comprises processing the modulation signal to provide the linearized modulation signal based on the equation:
Δ
N
FN
-
OPLL
=
-
N
2
Δ
N
PLL
-
N
2
N
0
-
N
0
,
wherein ΔN FN-OPLL is the linearized modulation signal, ΔN PLL is the modulation signal, N 0 is the initial fractional divide value, and N 2 is the control value.
19. The method of claim 17 wherein processing the modulation signal comprises processing the modulation signal to provide the linearized modulation signal based on an approximation of the equation:
Δ
N
FN
-
OPLL
=
-
N
2
Δ
N
PLL
-
N
2
N
0
-
N
0
,
wherein ΔN FN-OPLL is the linearized modulation signal, ΔN PLL is the modulation signal, N 0 is the initial fractional divide value, and N 2 is the control value.
20. The method of claim 17 wherein processing the modulation signal comprises processing the modulation signal to provide the linearized modulation signal based on the equation:
Δ
N
FN
-
OPLL
=
N
2
Δ
N
PLL
+
N
2
N
0
-
N
0
,
wherein ΔN FN-OPLL is the linearized modulation signal, ΔN PLL is the modulation signal, N 0 is the initial fractional divide value, and N 2 is the control value.
21. The method of claim 17 wherein processing the modulation signal comprises processing the modulation signal to provide the linearized modulation signal based on an approximation of the equation:
Δ
N
FN
-
OPLL
=
N
2
Δ
N
PLL
+
N
2
N
0
-
N
0
,
wherein ΔN FN-OPLL is the linearized modulation signal, ΔN PLL is the modulation signal, N 0 is the initial fractional divide value, and N 2 is the control value.