Low resistance integrated MOS structure
View Patent ↗The present invention is related to a metal-oxide semiconductor field-effect transistor (MOSFET) having a symmetrical layout such that the resistance between drains and sources is reduced, thereby reducing power dissipation. Drain pads, source pads, and gates are placed on the MOSFET such that the distances between drains, sources, and gates are optimized to reduce resistance and power dissipation. The gates may be arranged in a trapezoidal arrangement in order to maximize a ratio of the gate widths to gate lengths for current driving while reducing resistance and power dissipation.
1. A metal-oxide semiconductor field-effect transistor (MOSFET) for reducing power dissipation, the MOSFET comprising:
a first plurality of gates arranged in a substantially trapezoidal arrangement;
a second plurality of gates arranged in a substantially trapezoidal arrangement;
a drain region in proximity to the first and second plurality of gates;
a source region in proximity to the first and second plurality of gates; and
wherein the first and second substantially trapezoidal arrangements of the plurality of gates are substantially symmetrical with one another generally about an axis.
2. The MOSFET of claim 1 , wherein the axis is an XY-axis.
3. The MOSFET of claim 1 , wherein the axis is an XY-axis and the first and second substantially trapezoidal arrangements of the plurality of gates are symmetrical with one another generally about the XY-axis.
4. The MOSFET of claim 1 , wherein the axis is a YX-axis.
5. The MOSFET of claim 1 , wherein the axis is a YX-axis and the first and second substantially trapezoidal arrangements of the plurality of gates are symmetrical with one another generally about the YX-axis.
6. The MOSFET of claim 1 , wherein each of the drain region and the source region comprises a plurality of pads.
7. The MOSFET of claim 6 , wherein the number of the plurality of drain pads is equal to the number of the plurality of source pads.
8. The MOSFET of claim 6 , wherein the plurality of drain pads and the plurality of source pads are arranged generally about an XY-axis.
9. The MOSFET of claim 8 , wherein the axis is the XY-axis.
10. The MOSFET of claim 6 , wherein the plurality of drain pads and the plurality of source pads are arranged generally about an YX-axis.
11. The MOSFET of claim 10 , wherein the axis is the YX-axis.
12. The MOSFET of claim 1 , wherein the drain region is substantially outside an area of the first and second substantially trapezoidal arrangements of the plurality of gates.
13. The MOSFET of claim 1 , wherein the source region is substantially inside an area of the first and second substantially trapezoidal arrangements of the plurality of gates.
14. The MOSFET of claim 1 , wherein the first and second plurality of gates are arranged in a substantially isosceles trapezoidal arrangement.
15. The MOSFET of claim 1 , wherein the first and second plurality of gates are arranged in an isosceles trapezoidal arrangement.
16. The MOSFET of claim 1 , wherein the MOSFET is an n-type metal-oxide semiconductor (NMOS) transistor.
17. The MOSFET of claim 1 , wherein the MOSFET is a p-type metal-oxide semiconductor (PMOS) transistor.
18. The MOSFET of claim 1 , wherein the MOSFET is configured as a system on a chip.
19. The MOSFET of claim 1 , wherein the MOSFET is configured as a very large scale integration (VLSI) circuit.
20. The MOSFET of claim 1 , wherein the first plurality of gates and second plurality of gates are arranged to maximize a ratio of the gate widths to gate lengths.
21. A metal-oxide semiconductor field-effect transistor (MOSFET) for reducing power dissipation, the MOSFET comprising:
a first plurality of gates arranged in a substantially trapezoidal arrangement;
a second plurality of gates arranged in a substantially trapezoidal arrangement;
a third plurality of gates arranged in a substantially trapezoidal arrangement;
a fourth plurality of gates arranged in a substantially trapezoidal arrangement;
a first drain region in proximity to the first and second substantially trapezoidal arrangements of the plurality of gates;
a source region in proximity to the first, second, third and fourth substantially trapezoidal arrangements of the plurality of gates;
a second drain region in proximity to the third and fourth substantially trapezoidal arrangements of the plurality of gates;
wherein the first and second substantially trapezoidal arrangements of the plurality of gates are substantially symmetrical with one another generally about an axis; and
wherein the third and fourth substantially trapezoidal arrangements of the plurality of gates are substantially symmetrical with one another generally about the axis.
22. The MOSFET of claim 21 , wherein the axis is an XY-axis.
23. The MOSFET of claim 21 , wherein the axis is an YX-axis.
24. The MOSFET of claim 21 , wherein each of the first drain region, second drain region, and the source region comprises a plurality of pads.
25. The MOSFET of claim 24 , wherein the plurality of drain pads and the plurality of source pads are arranged generally about the axis.
26. The MOSFET of claim 21 , wherein the first drain region is generally outside an area of the first and second substantially trapezoidal arrangements of the plurality of gates.
27. The MOSFET of claim 21 , wherein the second drain region is substantially outside an area of the third and fourth substantially trapezoidal arrangements of the plurality of gates.
28. The MOSFET of claim 21 , wherein the source region is substantially inside an area of the first, second, third, and fourth substantially trapezoidal arrangements of the plurality of gates.
29. The MOSFET of claim 21 , wherein the first, second, third and fourth plurality of gates are arranged in a substantially isosceles trapezoidal arrangement.
30. The MOSFET of claim 21 , wherein the MOSFET is an n-type metal-oxide semiconductor (NMOS) transistor.
31. The MOSFET of claim 21 , wherein the MOSFET is a p-type metal-oxide semiconductor (PMOS) transistor.
32. The MOSFET of claim 21 , wherein the first, second, third, and fourth plurality of gates are arranged to maximize a ratio of the gate widths to gate lengths.
33. A power metal-oxide semiconductor field-effect transistor (MOSFET) for reducing power dissipation, the MOSFET comprising:
at least a first set of gates arranged in a substantially trapezoidal arrangement;
at least a second set of gates arranged in a substantially trapezoidal arrangement;
a drain region in proximity to the at least first and second set of gates;
a source region in proximity to the at least first and second set of gates; and
wherein the at least first and second set of substantially trapezoidal arrangements of the plurality of gates are substantially symmetrical with one another generally about an axis.
34. The MOSFET of claim 33 , wherein the axis is an XY-axis.
35. The MOSFET of claim 33 , wherein the axis is an YX-axis.
36. A metal-oxide semiconductor field-effect transistor (MOSFET) for reducing power dissipation, the MOSFET comprising:
a first plurality of gates arranged in a substantially trapezoidal arrangement;
a second plurality of gates arranged in a substantially trapezoidal arrangement;
a third plurality of gates arranged in a substantially trapezoidal arrangement;
a fourth plurality of gates arranged in a substantially trapezoidal arrangement;
a first drain region in proximity to the first and second substantially trapezoidal arrangements of the plurality of gates;
a source region in proximity to the first, second, third and fourth substantially trapezoidal arrangements of the plurality of gates;
a second drain region in proximity to the third and fourth substantially trapezoidal arrangements of the plurality of gates; and
wherein the first, second, third, and fourth substantially trapezoidal arrangements of the plurality of gates are substantially symmetrical with one another generally about the X, Y, XY and YX-axes.