Serialized secondary bus architecture

1. A system comprising:

a low pin count (LPC) bus operating according to an LPC protocol;

an I/O controller coupled to the LPC bus;

a second bus coupled to the I/O controller, wherein the second bus has a reduced pin count relative to the LPC bus and operates according to a second bus protocol; and

a plurality of devices coupled to the second bus;

wherein the I/O controller is configured to receive LPC bus transactions from the LPC bus, wherein the LPC bus transactions comprise device identification information identifying which of the plurality of devices are targeted by the LPC bus transactions;

wherein the I/O controller is further configured to translate the received LPC bus transactions into corresponding second bus transactions, wherein the corresponding second bus transactions comprise the device identification identifying which of the plurality of devices are targeted by the LPC bus transactions, and transmit the corresponding second bus transactions onto the second bus;

wherein each of the plurality of devices is configured to:

receive the corresponding second bus transactions; and

respond to the received corresponding second bus transaction that comprises device identification information identifying the device receiving the corresponding second bus transaction;

wherein the plurality of devices appear to the system as if they were transmitting and receiving data through respective LPC interfaces;

wherein the I/O controller includes a processing unit configured to initiate bus transactions on the second bus; and

wherein the I/O controller further includes a bus arbitration unit configured to arbitrate ownership of the second bus between the processing unit and the LPC bus.

2. The system of claim 1 , wherein the I/O controller is configured to receive bus transactions from the plurality of devices, and wherein the I/O controller is further configured to translate the received bus transactions into LPC bus transactions, and transmit the LPC bus transactions onto the LPC bus.

3. The system of claim 1 , wherein the I/O controller is a Super I/O integrated circuit device.

4. The system of claim 1 , wherein the second bus is a three-wire bus.

5. The system of claim 1 , wherein the plurality of devices comprise a low bandwidth device.

6. The system of claim 1 , wherein the plurality of devices comprise at least two of a parallel port, a serial port, a mouse interface, a universal asynchronous receiver-transmitter (UART), a trusted platform module (TPM), an infrared interface, a thermal sensor, a keyboard controller, and floppy disk controller.

7. The system of claim 1 , wherein the plurality of devices comprise a TPM, wherein the at least one device further comprises an interface for interfacing between the second bus and the TPM.

8. The system of claim 1 , wherein the second bus is configured to support data transfers, clocking, interrupt, broadcasts, and DMA requests between the I/O controller and the plurality of devices.

9. A circuit board, comprising:

a logic chipset;

a first bus coupled to the logic chipset, and configured to operate according to a first bus protocol;

an I/O controller coupled to the first bus;

a second bus coupled to the I/O controller, and configured to operate according to a second bus protocol, wherein the second bus has a reduced pin count relative to the first bus; and

a plurality of low bandwidth devices coupled to the second bus, wherein the low bandwidth devices comprise two or more of: a parallel port, a serial port, a mouse interface, a universal asynchronous receiver-transmitter (UART), a TPM, an infrared interface, a thermal sensor, a keyboard controller, and floppy disk controller;

wherein the I/O controller is configured to receive bus transactions from the first bus, wherein each bus transaction of at least a subset of the received bus transactions comprises respective device identification information identifying a corresponding respective low bandwidth device of the plurality of low bandwidth devices;

wherein the I/O controller is further configured to translate the received bus transactions into corresponding second bus transactions, wherein each second bus transaction of at least a subset of the corresponding second bus transactions comprises the respective device identification information identifying the corresponding respective low bandwidth device, and forward the corresponding second bus transactions onto the second bus;

wherein the plurality of low bandwidth devices are configured to receive the corresponding second bus transactions; and

wherein each corresponding respective low bandwidth device of the plurality of low bandwidth devices is configured to respond to the received corresponding second bus transaction that comprises the respective device identification information identifying the corresponding respective low bandwidth device receiving the corresponding second bus transaction;

wherein the low bandwidth devices appear to the logic chipset as if they were transmitting and receiving data through respective LPC interfaces;

wherein the I/O controller includes a processing unit configured to initiate bus transactions for the plurality of low bandwidth devices coupled to the second bus;

wherein the I/O controller further includes a bus arbitration unit configured to arbitrate ownership of the second bus between the processing unit and the first bus; and

wherein the first bus is an LPC bus, and the second bus has a reduced pin count relative to the LPC bus.

10. The circuit board of claim 9 , wherein the I/O controller is a Super I/O integrated circuit device.

11. The circuit board of claim 9 , wherein the second bus is a three-wire bus.

12. The circuit board of claim 9 , wherein the logic chipset is a Southbridge.

13. A method for communicating with a plurality of low bandwidth devices on a computer system motherboard, the method comprising:

transmitting LPC transactions from a logic chipset onto a low pin count (LPC) bus operating according to an LPC bus protocol;

receiving the transmitted LPC transactions at an I/O controller coupled to the LPC bus, wherein the LPC transactions comprise first identification information identifying at least one device of the plurality of low bandwidth devices;

translating the received LPC transactions to corresponding second bus transactions in the I/O controller, wherein the corresponding second bus transactions comprise the first identification information;

transmitting the corresponding second bus transactions over a second bus operating according to a second bus protocol, wherein the second bus has a reduced pin count relative to the LPC bus and the plurality of low bandwidth devices being coupled to the second bus;

receiving the corresponding second bus transactions at the at least one device coupled to the second bus; and the at least one device performing an operation at least in response to receiving the first identification information;

wherein the at least one device appears to the logic chipset as if it were transmitting and receiving data through an LPC interface;

initiating bus transactions in a processing unit of the I/O controller for the at least one device coupled to the second bus; and

arbitrating ownership of the second bus between the processing unit and the LPC bus.

14. A system comprising:

a low pin count (LPC) bus configured to operate according to an LPC bus protocol;

an I/O controller coupled to the LPC bus;

a second bus coupled to the I/O controller, and configured to operate according to a second bus protocol, wherein the second bus has a reduced pin count relative to the LPC bus; and

a plurality of devices coupled to the second bus, wherein one of the plurality of devices is a trusted platform module (TPM);

wherein the I/O controller is configured to receive LPC bus transactions from the LPC bus, wherein each transaction of at least a subset of the LPC bus transactions comprises respective identification information identifying a respective one of the plurality of devices;

wherein the I/O controller is further configured to translate the received LPC bus transactions into corresponding second bus transactions, and transmit the corresponding second bus transactions onto the second bus, wherein each corresponding second bus transaction comprises the respective identification information comprised in that LPC bus transaction of the LPC bus transactions to which the corresponding second bus transaction corresponds;

wherein the I/O controller includes a processing unit configured to initiate bus transactions for the plurality of devices coupled to the second bus; and

wherein the I/O controller further includes a bus arbitration unit configured to arbitrate ownership of the second bus between the processing unit and the LPC bus;

wherein the plurality of devices appear to the system as if they were transmitting and receiving data through respective LPC interfaces.

15. A device which operates as an I/O controller for a low pin count (LPC) bus, the device comprising:

a first port configured to couple to the low pin count (LPC) bus operating according to an LPC protocol;

a second port configured to couple to a second bus, wherein the second bus has a reduced pin count relative to the LPC bus and operates according to a second bus protocol; and

a plurality of devices coupled to the second bus;

wherein the device is configured to receive LPC bus transactions from the LPC bus, wherein the LPC bus transactions comprise device identification information identifying which of the plurality of devices are targeted by the LPC bus transactions;

wherein the device is further configured to translate the received LPC bus transactions into corresponding second bus transactions, and transmit the corresponding second bus transactions onto the second bus, wherein the second bus transactions comprise the device identification information identifying which of the plurality of devices are targeted by the LPC bus transactions;

wherein the plurality of devices appear to a processing unit coupled to the LPC bus as if they were transmitting and receiving data through respective LPC interfaces;

wherein the device includes a processing unit configured to initiate bus transactions for the plurality of devices coupled to the second bus; and

wherein the device further includes a bus arbitration unit configured to arbitrate ownership of the second bus between the processing unit and the LPC bus.