IP Library Granted Patent US 7,624,260
Granted Patent B2
US 7,624,260 · App. 11/418,481 · Granted Nov 24, 2009

System executing a fast boot wake-up

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,624,260
App. No.
11/418,481
Granted
Nov 24, 2009
Kind
B2
Abstract

A processing system is set forth that includes a processor, read only memory storing an operating system image file accessible by the processor, and random access memory that is also accessible by the processor. The processing system also includes a boot program that is executable by the processor to initialize the processing system in response, for example, to a power-on event, reset event, or a wake-up event. A power-on event occurs when power is initially provided to the processing system while a wake-up event occurs when the processing system is to exit a low-power mode of operation. A reset event occurs when, for example, a fault is detected that causes the system to restart. The boot program selectively performs a full boot copy of the operating system image file from the read only memory to the random access memory or a fast boot copy of only predetermined portions of the operating system image file from the read only memory to the random access memory. For example, the boot program may execute the full boot copy operation in response to the power-on event and the fast boot copy operation in response to the wake-up event and/or reset event. Further, the boot program may limit execution of the fast boot copy operation to those instances in which the random access memory passes an integrity check of the contents of one or more areas containing selected portions of the operating system copied from the read only memory during a prior full boot copy operation.

Claims (32)

1. A processing system comprising:

a processor responsive to a reset signal for directing initial execution of a program at a reset vector;

self-refreshing random access memory accessible by the processor;

read only memory storing an operating system image file, an initial program loader beginning at the reset vector, and startup code loaded into the self-refreshing random access memory in response to execution of the initial program loader;

a power control system responsive to power commands and/or power control signals to direct the system into a low-power mode and to wake-up the system from the low-power mode, where the processor and self-refreshing random access memory are each directed into a low-power consumption state during the low-power mode, and where the power control system generates the reset signal to the processor to direct the system to wake-up from the low-power mode, where the processor and self-refreshing random access memory are directed out of their respective low-power states to an operating power consumption state when the system wakes-up from the low-power mode;

where either the initial program loader or the startup code selectively performs a full boot copy of the operating system image file from the read only memory to the self-refreshing random access memory in response to an initial power-up of the system, or a fast boot copy of only predetermined portions of the operating system image file from the read only memory to the self-refreshing random access memory when waking-up from the low-power mode.

2. The processing system of claim 1 , where the self-refreshing random access memory comprises dynamic random access memory.

3. The processing system of claim 1 , where the self-refreshing random access memory comprises dynamic random access memory and where the power control system responds to a power down event, as indicated by the power commands and/or power control signals, to direct the system to enter a low-power mode in which the dynamic random access memory is in a self-refresh mode and power is removed from the processor.

4. The processing system of claim 3 , where either the initial program loader or the startup code is executed to perform at least a partial check of the content of the dynamic random access memory as the system exits the low-power mode, and where either the initial program loader or the startup code is executed to use a result of the check to determine whether a full boot copy operation or a fast boot copy operation is executed.

5. The processing system of claim 1 , where either the initial program loader or the startup code is executed to perform at least a partial check of the contents of the self-refreshing random access memory to select whether the full boot copy operation or the fast boot copy operation will be executed.

6. The processing system of claim 1 , where either the initial program loader or the startup code is executed to perform a checksum operation on at least a portion of the contents of the random access memory to select whether the full boot copy operation or the fast boot copy operation is executed.

7. The processing system of claim 6 , where the checksum operation is performed on the data structure of data stored in the random access memory.

8. The processing system of claim 1 , where the operating system image file comprises at least two image filesystems including a primary image filesystem and a secondary image filesystem.

9. The processing system of claim 8 , where both the primary image filesystem and the secondary image filesystem are copied from the read only memory to the self-refreshing random access memory when the startup code is executed to perform a full boot copy, and where only the primary image filesystem of the primary and secondary image filesystems is copied from the read only memory to the self-refreshing random access memory when the startup program is executed to perform a fast boot copy.

10. The processing system of claim 1 , where the operating system image file comprises:

a kernel pro gram;

a further program selected from the group consisting of a peripheral driver, a dynamic link library, and a system application.

11. The processing system of claim 10 , where the further program and the kernel program are copied from the read only memory to the self-refreshing random access memory when the startup code is executed to perform a full boot copy, and where the startup code is executed to perform a fast boot copy by copying at least a portion of the kernel program from the read only memory to the self-refreshing random access memory without copying the further program from the read only memory to the random access memory.

12. A processing system comprising:

a processor responsive to a reset signal for directing initial execution of a program at a reset vector;

read only memory storing an operating system image file accessible by the processor;

dynamic random access memory accessible by the processor;

a power control system responsive to a power down event to direct the system to enter a low-power mode in which the dynamic random access memory is in a self-refresh mode and the processor is powered off, and where the power control system is further responsive to a wake-up event as well as to an initial power up event to direct the system to reset the processor by generating the reset signal, where the dynamic random access memory and processor are directed to operational power consumption states in response to the wake-up event;

a boot program, beginning at the reset vector, that is executable by the processor to initialize the processing system when the dynamic random access memory and processor are in their operational power consumption states, where the boot program performs a full boot copy of the operating system image file from the read only memory to the dynamic random access memory in response to the initial power-up of the system, and where the boot program performs a fast boot copy of only predetermined portions of the operating system image file from the read only memory to the dynamic random access memory when the system exits the low-power mode in response to one or more predetermined conditions.

13. The processing system of claim 12 , where the boot program is executed to perform at least a partial check of the contents of the dynamic random access memory when the system exits the low-power mode, and where the boot program uses a result of the check as the one or more predetermined conditions.

14. The processing system of claim 13 , where a checksum operation is performed on the data structure of data stored in the dynamic random access memory.

15. The processing system of claim 12 , where the operating system image file comprises at least two image filesystems including a primary image filesystem and a secondary image filesystem.

16. The processing system of claim 15 , where both the primary image filesystem and the secondary image filesystem are copied from the read only memory to the dynamic random access memory when the boot program is executed to perform the full boot copy, and where only the primary image filesystem of the primary and secondary image filesystems is copied from the read only memory to the dynamic random access memory when the boot program is executed to perform the fast boot copy.

17. The processing system of claim 12 , where the operating system image file comprises:

a kernel program;

a further program selected from the group consisting of a peripheral driver, a dynamic link library, and a system application.

18. The processing system of claim 17 , where the further program and the kernel program are copied from the read only memory to the dynamic random access memory when the boot program is executed to perform a full boot copy, and where the boot program is executed to perform a fast boot copy by copying at least a portion of the kernel program from the read only memory to the dynamic random access memory without copying the further program from the read only memory to the dynamic random access memory.

Assignments (13)
NUNC PRO TUNC ASSIGNMENT Recorded Jun 19, 2023
From: BLACKBERRY LIMITED
To: MALIKIE INNOVATIONS LIMITED
Reel/Frame 064270/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 16, 2023
From: BLACKBERRY LIMITED
To: MALIKIE INNOVATIONS LIMITED
Reel/Frame 064104/0103 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 22, 2020
From: 2236008 ONTARIO INC.
To: BLACKBERRY LIMITED
Reel/Frame 053313/0315 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 4, 2014
From: 8758271 CANADA INC.
To: 2236008 ONTARIO INC.
Reel/Frame 032607/0674 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 4, 2014
From: QNX SOFTWARE SYSTEMS LIMITED
To: 8758271 CANADA INC.
Reel/Frame 032607/0943 →
CHANGE OF ADDRESS Recorded Feb 27, 2012
From: QNX SOFTWARE SYSTEMS LIMITED
To: QNX SOFTWARE SYSTEMS LIMITED
Reel/Frame 027768/0961 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 9, 2011
From: 7801769 CANADA INC.
To: QNX SOFTWARE SYSTEMS LIMITED
Reel/Frame 026883/0553 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 9, 2011
From: QNX SOFTWARE SYSTEMS GMBH & CO. KG
To: 7801769 CANADA INC.
Reel/Frame 026883/0544 →
REGISTRATION Recorded Feb 28, 2011
From: QNX SOFTWARE SYSTEMS GMBH & CO. KG
To: QNX SOFTWARE SYSTEMS GMBH & CO. KG
Reel/Frame 025863/0398 →
CHANGE OF SEAT Recorded Feb 28, 2011
From: QNX SOFTWARE SYSTEMS GMBH & CO. KG
To: QNX SOFTWARE SYSTEMS GMBH & CO. KG
Reel/Frame 025863/0434 →
PARTIAL RELEASE OF SECURITY INTEREST Recorded Jun 3, 2010
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: HARMAN INTERNATIONAL INDUSTRIES, INCORPORATED; QNX SOFTWARE SYSTEMS (WAVEMAKERS), INC.; QNX SOFTWARE SYSTEMS GMBH & CO. KG
Reel/Frame 024483/0045 →
SECURITY AGREEMENT Recorded May 8, 2009
From: HARMAN INTERNATIONAL INDUSTRIES, INCORPORATED; BECKER SERVICE-UND VERWALTUNG GMBH; CROWN AUDIO, INC.; HARMAN BECKER AUTOMOTIVE SYSTEMS (MICHIGAN), INC.; HARMAN BECKER AUTOMOTIVE SYSTEMS HOLDING GMBH; HARMAN BECKER AUTOMOTIVE SYSTEMS, INC.; HARMAN CONSUMER GROUP, INC.; HARMAN DEUTSCHLAND GMBH; HARMAN FINANCIAL GROUP LLC; HARMAN HOLDING GMBH & CO. KG; HARMAN MUSIC GROUP, INCORPORATED; HARMAN SOFTWARE TECHNOLOGY INTERNATIONAL BETEILIGUNGS GMBH; HARMAN SOFTWARE TECHNOLOGY MANAGEMENT GMBH; HBAS INTERNATIONAL GMBH; HBAS MANUFACTURING, INC.; INNOVATIVE SYSTEMS GMBH NAVIGATION-MULTIMEDIA; JBL INCORPORATED; LEXICON, INCORPORATED; MARGI SYSTEMS, INC.; QNX SOFTWARE SYSTEMS (WAVEMAKERS), INC.; QNX SOFTWARE SYSTEMS CANADA CORPORATION; QNX SOFTWARE SYSTEMS CO.; QNX SOFTWARE SYSTEMS GMBH; QNX SOFTWARE SYSTEMS GMBH & CO. KG; QNX SOFTWARE SYSTEMS INTERNATIONAL CORPORATION; QNX SOFTWARE SYSTEMS, INC.; XS EMBEDDED GMBH (F/K/A HARMAN BECKER MEDIA DRIVE TECHNOLOGY GMBH)
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 022659/0743 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 17, 2006
From: ETHIER, SHERIDAN; MARTIN, RANDY; BURGESS, COLIN; STECHER, BRIAN
To: QNX SOFTWARE SYSTEMS GMBH & CO. KG
Reel/Frame 018141/0606 →