Abstracted host bus interface for complex high performance ASICs
View Patent ↗An interface is provided to couple an input/output device (e.g., a network interface unit) to one or more different host system buses without altering the configuration of the device (e.g., to include logic specific to the host buses). Functionality of the device (e.g., MTU size, error detection) is therefore independent of the host bus. Host bus logic for managing operation of the host bus is augmented with logic for translating between semantics of the interface and the host bus. Also, end-to-end verification of a complex ASIC in multiple configurations or environments can be performed over the interface without probing into the ASIC.
1. A complex Application Specific Integrated Circuit (ASIC) having an interface for electrically coupling the ASIC to any of multiple host computer system buses, the ASIC comprising:
an input/output component;
first two-way host bus logic configured to translate communications between the input/output component and a first host bus, the host bus logic comprising:
a request queue for issuing read requests and write requests from the input/output component to the first host bus;
a response queue for receiving from the first host bus responses to the read requests;
an acknowledgement queue for receiving from the first host bus acknowledgements of non-posted write requests;
host meta logic configured to:
convert a request from the input/output component into an appropriate bus transaction accepted by the first host bus;
convert a host bus transaction including response or acknowledgement received by the first host bus into a format accepted by the input/output component; and
issue a pseudo acknowledgement to the acknowledgement queue on the first host bus logic for non-posted write request if the first host bus does not implement an acknowledgement queue configured to issue acknowledgements of non-posted write 24 requests to the acknowledgement queue on the first host bus logic;
a table to map an operation's operation identifier to the transaction identifiers of the corresponding first host bus transactions; and
a meta interface configured to concurrently convey the requests, the responses and the acknowledgements between the input/output component and the first host bus logic.
2. The complex ASIC of claim 1 , further comprising:
at least one additional host bus logic configured to translate communications between the input/output component and an additional host bus.
3. The complex ASIC of claim 1 , wherein the host meta logic is further configured to report to the input/output component completion of non-posted write requests in order with completion of posted write requests.
4. The complex ASIC of claim 1 , wherein the input/output component is a Network Interface Unit.