Pattern-dependent phase detector for clock recovery
View Patent ↗A phase detector apparatus and method used for clock recovery from a data signal is provided. The phase detector provides phase correction signals to a clock signal generator, where the phase correction signals are only generated if a predetermined data sample pattern is observed. In particular, the predetermined data sample pattern is preferably a transition from one to zero. Thus, transitions from zero to one will not provide a valid phase update output signal, even though a transition has occurred. In other embodiments the predetermined data sample pattern is preferably a one to zero transition preceded by an additional logic one sample.
1. An apparatus for providing phase correction signals to a clock signal generator, comprising:
a data signal sampler that provides signal samples at twice a symbol-rate in response to a local clock signal, wherein the signal samples comprise at least a first signal sample and a second signal sample that are separated by a symbol period, and an intervening signal sample occurring between the first and second signal samples;
a digital logic circuit for processing the first and second signal samples and the intervening signal sample to (i) identify the occurrence of at least one of 0 to 1 transitions and 1 to 0 transitions, (ii) generate a pattern-dependent phase correction signal upon the occurrence of only one of 0 to 1 transitions and 1 to 0 transitions.
2. The apparatus of claim 1 wherein the data signal sampler comprises a first and second memory element for storing the first signal sample and second signal sample, respectively, and a third memory element for storing the intervening signal sample.
3. The apparatus of claim 2 wherein the memory elements are flip-flops.
4. The apparatus of claim 3 wherein the first and second memory elements are triggered at a symbol rate by a first edge of a clock signal and the third memory element is triggered at a symbol rate by a second edge of a clock signal.
5. The apparatus of claim 4 further comprising a fourth memory element for storing a re-timed version of the intervening signal sample.
6. The apparatus of claim 1 wherein the digital signal sampler is a 1 bit analog to digital converter (ADC).
7. The apparatus of claim 6 wherein the 1 bit ADC comprises a thresholding device having a predetermined threshold.
8. The apparatus of claim 1 wherein the digital signal sampler is a multi-bit ADC.
9. The apparatus of claim 8 wherein the multi-bit ADC comprises two thresholding devices having different thresholds.
10. The apparatus of claim 1 wherein the signal samples further comprise a third signal sample separated from one of the first and second signal samples by a symbol period, and wherein the digital logic circuit processes the first, second and third signal samples to identify the occurrence of a predetermined signal transition.
11. The apparatus of claim 1 wherein the data signal sampler comprises a first sample path for sampling data on a rising edge of a clock signal, and a second path for sampling data on a falling edge of a clock signal.
12. A method of providing phase correction signals to a clock signal generator, comprising the steps of:
(i) obtaining a received signal sample sequence;
(ii) determining a relative phase between a clock signal and a received data signal in response to the received signal sample sequence;
(iii) determining whether a data transition has occurred in response to the received signal sample sequence; and,
(iv) determining whether the received signal sample sequence is equal to a predetermined signal sample sequence, and if so, generating a pattern dependent phase correction signal in response to the determined relative phase, wherein the predetermined signal sample sequence is a transition from 1 to 0.
13. The method of claim 12 wherein the step of obtaining a received signal sample sequence comprises determining whether a received signal is above or below a first threshold.
14. The method of claim 13 wherein the step of obtaining the received signal sample sequence further comprises determining whether the received signal is above or below a second threshold.
15. The method of claim 12 wherein the received signal sample sequence comprises samples taken at a rate equal to twice the symbol rate.
16. The method of claim 12 wherein the step of determining whether a transition has occurred comprises comparing samples separated by one symbol period.
17. The method of claim 12 wherein the step of determining whether a transition has occurred comprises determining that a high to low transition has occurred.
18. The method of claim 12 wherein the step of determining whether the received signal sample sequence is equal to a predetermined signal sample sequence comprises determining whether at least two samples separated by one symbol period precede the data transition.
19. A method of providing phase correction signals to a clock signal generator
comprising the steps:
(i) obtaining a received signal sample sequence, wherein the signal sample sequence contains at least some multi-bit samples;
(ii) determining a relative phase between a clock signal and a received data signal in response to the received signal sample sequence;
(iii) determining whether a predetermined data transition has occurred in response to the multi-bit samples, wherein the predetermined data transition is a transition from one to zero, and, if so,
(iv) generating a pattern dependent phase correction signal in response to the determined relative phase.
20. The method of claim 19 wherein the step of determining whether a predetermined data transition has occurred comprises insuring that the data transition involves a transition from the highest signal sample value to the lowest signal sample value.