Control signal interface circuit for computer memory modules
View Patent ↗The invention is an electronic circuit designed for incorporation on computer memory modules such as DDR DIMMs. It couples control signals such as address bits, bank selects, enable and even clock signals between the module input connector and the memory devices. The circuit provides low propagation delay, fast rise and fall times with no overshoot or undershoot, and significantly improves timing control compared to memory modules of the present art. Capacitive loading on the motherboard is typically much less than that provided by a single memory device input and is independent of the number of memory devices per bank or the number of banks of memory devices on the memory module. For multiple memory modules connected to the memory bus, capacitive loading is essentially N times the equivalent loading for a single memory module.
1. A circuit comprising:
a low loading input buffer coupled to a control signal input and providing a buffer output;
an output driver coupled to the buffer output and to an integrated circuit;
wherein the output driver comprises a gain circuit for providing high speed pull-up and pull down of the input buffer output, and a clamp circuit for preventing forward bias.
2. The circuit of claim 1 wherein the integrated circuit is a memory.
3. The circuit of claim 2 wherein the input buffer comprises bipolar transistor with associated gate, emitter, and collector circuitry.
4. The circuit of claim 3 wherein the output driver comprise is a push-pull structure.
5. The circuit of claim 4 wherein the push-pull structure comprises a pair of bipolar junction transistors.
6. The circuit of claim 5 wherein the buffer is coupled to the output driver via an RC circuit.
7. The circuit of claim 6 further including a plurality of output drivers coupled to the input buffer and each coupled to associated memory banks.